TCAD simulation study of independent gate junctionless FET-based flash memory

Author(s):  
R. Srinivasan ◽  
R. Ambika
2009 ◽  
Vol 518 (5) ◽  
pp. 1595-1598 ◽  
Author(s):  
Shu-Tong Chang ◽  
Wei-Ching Wang ◽  
Chang-Chun Lee ◽  
Jacky Huang

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1775
Author(s):  
Jae-Min Sim ◽  
Myounggon Kang ◽  
Yun-Heub Song

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.


Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 829
Author(s):  
Taejin Jang ◽  
Suhyeon Kim ◽  
Jeesoo Chang ◽  
Kyung Kyu Min ◽  
Sungmin Hwang ◽  
...  

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.


2011 ◽  
Vol 27 (1) ◽  
pp. 339-348 ◽  
Author(s):  
Kong Boon Yeap ◽  
Ehrenfried Zschech ◽  
Ude D. Hangen ◽  
Thomas Wyrobek ◽  
Lay Wai Kong ◽  
...  

Abstract


Sign in / Sign up

Export Citation Format

Share Document