Investigation of solder creep behavior on wafer level CSP under thermal cycling loading

Author(s):  
Kai-Chiang Wu ◽  
Kuo-Ning Chiang
2021 ◽  
Author(s):  
Abdullah Fahim ◽  
S M Kamrul Hasan ◽  
Jeffrey Suhling ◽  
Pradeep Lall

Author(s):  
Abdullah Fahim ◽  
S. M. Kamrul Hasan ◽  
Jeffrey C. Suhling ◽  
Pradeep Lall

Abstract Solder joints in electronic packages are frequently exposed to thermal cycling environment. Such exposures can occur in real life application as well as in accelerated thermal cycling tests used for the fatigue behavior characterization. Because of temperature variations and CTE mismatches of the assembly materials, cyclic temperature leads to damage accumulation and material property evolution in the solder joints. This eventually results in crack initiation, and subsequent crack growth and failure. In this study, the nanoindentation technique was used to understand the evolution of mechanical properties (modulus, hardness and creep behavior) of SAC305 BGA solder joints and Cu pad subjected to thermal cycling loading for various durations. In addition, microstructural changes in those joints that occur during thermal cycling were observed using both SEM and optical microscopy. BGA solder joint strip specimens were first prepared by cross sectioning BGA assemblies followed by surface polishing to facilitate SEM imaging and nanoindentation testing. The strip specimens were chosen to contain several single grain solder joints. This enabled large regions of solder material with equivalent mechanical behavior, which could then be indented several times after various durations of cycling. After preparation, the solder joint strip samples were thermally cycled from T = −40 to 125 °C in an environmental chamber. At various points in the cycling (e.g. after 0, 50, 100, and 250 cycles), the package was taken out from the chamber, and nanoindentation was performed on each single grain joint and joint Cu pads to obtain the modulus, hardness, and creep behavior at 25 °C. This allowed the evolution of the mechanical properties with the duration of thermal cycling to be determined. Moreover, microstructural changes were also observed after various durations of cycling using optical microscopy. From the nanoindentation test results, it was found that the modulus and hardness of the SAC305 solder joints dropped significantly with thermal cycling. However, the Cu pad did not show any change in the mechanical behavior during cycling. Moreover, the nanoindentation creep test results showed significant increases in the creep deformation for solder joints whereas Cu pad did now show any significant changes in creep behavior when both of them were subjected to thermal cycling up to 250 cycles.


Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.


2001 ◽  
Vol 9 (4) ◽  
pp. 279-286 ◽  
Author(s):  
R.S. Sundar ◽  
K. Kitazono ◽  
E. Sato ◽  
K. Kuribayashi

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.


2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.


Materialia ◽  
2020 ◽  
Vol 14 ◽  
pp. 100913 ◽  
Author(s):  
Xiaotong Guo ◽  
Weiwei Zheng ◽  
Wenrui An ◽  
Stoichko Antonov ◽  
Longfei Li ◽  
...  

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