Effect of Local Grain Distribution and Enhancement on Edgebond Applied Wafer-Level Chip-Scale Package (WLCSP) Thermal Cycling Performance

Conformal coating is commonly used for harsh environment to protect electronics from moisture and chemical contaminants. But the stresses imparted by the conformal coating can cause degradation to the package thermal cycle performance. Full coverage of the component with conformal coating material can prevent potential corrosion induced degradation but imply a local compression stress during thermal cycling, resulting a different thermal cycling performance compared to non-coated components. In this study, 8x8mm2 wafer level chip scale packages (WLCSP) were subjected to 5% NaCl aqueous spray test with and without full conformal coating, then thermal cycled from -40ºC to +125ºC. Weibull reliability statistics indicated that fully conformal coated components experience characteristic life cycle number reduction from 404 cycles to 307 cycles, a 24% lifetime reduction, comparing to no conformal coated, no salt spray test applied components. The correlation between crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and electro-backscattered diffraction, which revealed that the conformal coating induced a z-axis tension and compression strain during thermal cycling, resulting in an accelerated degradation at the solder interconnect. Linear Laser profilometer measurements showed that fully conformal coated samples experienced a higher z-axis height displacement change relative to non-conformal coated samples when exposed to 125 °C with 10 minutes dwell. To prevent this z-axis strain a reworkable edgebond adhesive was applied with full conformal coating configuration, which demonstrate an increase of characteristic lifecycle number to 2783 cycles, suggesting that the mitigation of the z-axis strain can vastly enhance the thermal cycling performance.

Download Full-text

Edgebond and Edgefill Induced Loading Effect on Large WLCSP Thermal Cycling Performance

Journal of Surface Mount Technology ◽

10.37665/smt.v33i2.10 ◽

2020 ◽

Vol 33 (2) ◽

pp. 22-27

Author(s):

Andy Hsiao ◽

Greg Baty ◽

Edward Ibe ◽

Karl Loh ◽

Steve Perng ◽

...

Keyword(s):

Thermal Cycling ◽

Degradation Mechanism ◽

Stress Component ◽

High Stress ◽

Cycling Performance ◽

Propagation Path ◽

Wafer Level ◽

Electron Backscattered Diffraction ◽

Mechanical Cycling ◽

Failure Location

Various external load conditions affecting components on electronic devices and modules are constant factors, which need to be considered for the component long-term reliability. Recently, to enhance the high stress component thermo-mechanical cycling performance, various types and configuration using edgebond and edgefill technology are introduced and tested. These applications induce a multi-axis loading condition, which alter the degradation mechanism and failure location during thermal cycling, which need closer investigation. In this study, high stress 12x12mm2 wafer level chip scale packages (WLCSP) were selected and subject to thermal cycling with full-edgebond, dot-edgebond and edgefill adhesive, which improves the characteristic lifecycle numbers base on the configurations, but altered the failure location due to different stress conditions. The -40 to 125oC thermal cycling profile revealed localized degradation per configuration during thermal cycling, showed a shift of the crack propagation path, based on full-edgebond, dot-edgebond and edgefill adhesive sample conditions. Through these series of observation, the interconnect thermal cycling degradation mechanisms are able to be explained. The correlation between the stress condition and microstructure are presented and discussed based on Electron backscattered diffraction (EBSD) analysis.

Download Full-text

Thermal Cycling Simulation and Sensitivity Analysis of Wafer Level Chip Scale Package with Integration of Metal-Insulator-Metal Capacitors

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2019.00234 ◽

2019 ◽

Author(s):

Yi Zhou ◽

Liangbiao Chen ◽

Yong Liu ◽

Suresh Sitaraman

Keyword(s):

Sensitivity Analysis ◽

Thermal Cycling ◽

Wafer Level ◽

Metal Insulator ◽

Metal Insulator Metal ◽

Chip Scale Package

Download Full-text

LORD SolderBrace™ Wafer Applied Coating for Improved Reliability and Throughput in WLCSP

International Symposium on Microelectronics ◽

10.4071/isom-2013-ta25 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000055-000060 ◽

Cited By ~ 1

Author(s):

George Sears ◽

Guoyun Tian ◽

Duy Le ◽

Heather Bradley

Keyword(s):

Thermal Cycling ◽

Polymer System ◽

Cost Effective ◽

Wafer Level ◽

Material Technology ◽

Joint Stress ◽

Chip Scale Package ◽

New Material ◽

Solder Fatigue ◽

Applied Coating

As more manufacturers look to increase the size of Wafer Level Chip Scale Package (WLCSP) dies and also look to decrease the ball pitch, the susceptibility of the die to fail during thermal cycling and drop shock testing increases. The stress conditions introduced during thermal cycling from the mismatches in Coefficients of Thermal Expansion (CTE) lead to solder fatigue. The failure of WLCSPs during drop shock is found at the solder/pad interface. The general solution to address solder fatigue during thermal cycling and solder joint stress at the copper pad interface has been capillary underfilling the chips after chip attachment. To address these issues, a new material from LORD Corporation – SolderBrace™ wafer applied coating, can be used to partially underfill the WLCSP die at the wafer level. This type of technology can be applied using existing equipment and processing techniques making these materials a more cost effective solution. This new material technology has enabled thermal cycling reliability improvements by replacing the final passivation layer with a new low CTE material as the partial underfill. This wafer applied partial underfill material technology has been successfully used to provide increased thermal cycling and drop shock reliability in WLCSPs using a number of different methods that have been previously described. The method to be discussed in this paper is a production process using a screen printed, photo defined polymer system that does not require any in-process post cure.

Download Full-text

Improving WLCSP Reliability Through Solder Joint Geometry Optimization

International Symposium on Microelectronics ◽

10.4071/isom-2013-wa45 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000546-000550 ◽

Cited By ~ 5

Author(s):

Boyd Rogers ◽

Chris Scanlan

Keyword(s):

Solder Joint ◽

Thermal Cycling ◽

Printed Circuit Board ◽

Geometry Optimization ◽

Circuit Board ◽

Wafer Level ◽

Joint Geometry ◽

Chip Scale Package ◽

Large Platform ◽

Board Level

The effects of solder joint geometry on wafer-level chip-scale package reliability have been studied both through simulations and board level reliability testing. In reliability tests on a 3.9×3.9mm2 die, an enhancement of nearly 2× in thermal cycling reliability was achieved by optimizing the solder joint and under-bump pad stack. In particular, undersizing the printed circuit board pad to produce a more spherical solder joint and reducing the polymer via size under the bump appear to be very important for improving thermal cycling results. Data collected here shows that joint geometry changes can be implemented without compromising drop performance. Methods learned were applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.

Download Full-text

Sample Preparation Challenges In WLCSP Epoxy Underfill Coating Removal

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0471 ◽

2012 ◽

Author(s):

Jason H. Lagar ◽

Rudolf A. Sia

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Vital Role ◽

Fault Isolation ◽

Wafer Level ◽

Chip Scale Package ◽

Coating Removal ◽

Customer Returns ◽

Preparation Techniques ◽

Mechanical Defect

Abstract Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.

Download Full-text

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽

10.3390/mi12030295 ◽

2021 ◽

Vol 12 (3) ◽

pp. 295

Author(s):

Pao-Hsiung Wang ◽

Yu-Wei Huang ◽

Kuo-Ning Chiang

Keyword(s):

Finite Element ◽

Thermal Cycling ◽

Glass Substrate ◽

High Speed ◽

Coefficient Of Thermal Expansion ◽

Three Dimensional ◽

Design Parameters ◽

Time To Failure ◽

Wafer Level ◽

Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Download Full-text