Comparative analysis of the CMOS 180nm technology-based flash ADC designs using dynamic comparator and TIQ comparator

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽

10.3390/s20185309 ◽

2020 ◽

Vol 20 (18) ◽

pp. 5309

Author(s):

Shengbiao An ◽

Shuang Xia ◽

Yue Ma ◽

Arfan Ghani ◽

Chan Hwang See ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

Supply Voltage ◽

Total Power ◽

Cmos Process ◽

Hybrid Architecture ◽

Sigma Delta Modulator ◽

Dynamic Comparator ◽

Flash Adc ◽

Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

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TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b1041.0782s219 ◽

2019 ◽

Vol 8 (2S2) ◽

pp. 226-229

Keyword(s):

Low Power ◽

Power Dissipation ◽

Low Voltage ◽

Supply Voltage ◽

Power Supply Voltage ◽

Large Power ◽

Flash Adc ◽

Analog To Digital ◽

Tiq Comparator ◽

The Impact

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

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A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.k1003.09811s19 ◽

2019 ◽

Vol 8 (11S) ◽

pp. 11-19

Keyword(s):

Comparative Analysis ◽

High Resolution ◽

Low Power ◽

Time Domain ◽

High Speed ◽

Sampling Rate ◽

Cmos Technology ◽

Digital Converter ◽

Flash Adc ◽

Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

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Reduced Complexity Linearity Improved Threshold Quantized Comparator Based Flash ADC

Journal of Circuits System and Computers ◽

10.1142/s0218126617500463 ◽

2016 ◽

Vol 26 (03) ◽

pp. 1750046 ◽

Cited By ~ 2

Author(s):

Prachi Palsodkar ◽

Pravin Dakhole ◽

Prasanna Palsodkar

Keyword(s):

Low Voltage ◽

Size Variation ◽

Standard Cell ◽

Hardware Complexity ◽

Large Area ◽

Flash Adc ◽

Low Voltage Operation ◽

Division Theorem ◽

Ladder Network ◽

Tiq Comparator

This paper describes a standard cell-based new approach of comparator design for flash ADC. Conventional flash ADC comparator consumes up to 60% of the power due to resistive ladder network and analog comparators. Threshold inverter quantized (TIQ) comparators reported earlier have improved speed and provide low-power, low-voltage operation. But they need feature size variation and have non-linearity issues. Here, a new standard cell comparator is proposed which retains all advantages of TIQ comparator and provides improved linearity with reduced hardware complexity. A 4-bit ADC designed using the proposed comparator requires 206 minimum-sized transistors and provides large area saving compared to previously proposed designs. Thermometer code is partitioned using algebraic division theorem. This conversion is used for mathematical modeling and complexity reduction of decoder circuit using semi-parallel organization of comparators. Circuit is designed using 90 nm technology which exhibits satisfactory performance even in process variation.

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