NEGATIVE RESISTANCE ACTIVE RESISTOR WITH IMPROVED LINEARITY AND FREQUENCY RESPONSE

2009 ◽  
Vol 18 (01) ◽  
pp. 1-10 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Frequency Response ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Original Method ◽  
Order Effects ◽  
Mos Transistors ◽  
Mos Transistor ◽  
Saturation Region ◽  
Linear Differential

An original active resistor circuit will be presented. The main advantages of the new proposed implementations are the improved linearity, small area consumption and improved frequency response. An original technique for linearizing the I(V) characteristic of the active resistor will be proposed, based on the utilization of a new linear differential amplifier, and on a current-pass circuit. The linearization of the original differential structure is achieved by compensating the quadratic characteristic of the MOS transistor operating in the saturation region by an original square-root circuit. The errors introduced by the second-order effects will be strongly reduced, while the circuit frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. In order to design a circuit having a negative equivalent resistance, an original method specific to the proposed implementation of the active resistor circuit will be presented. The circuit is implemented in 0.35 μm CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (± 500 mV) and a small value of the supply voltage (± 3 V).

scholarly journals Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Maneesha Gupta ◽  
Richa Srivastava ◽  
Urvashi Singh
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Order Effect ◽  
Floating Gate ◽  
Current Output ◽  
Mos Transistor ◽  
Differential Voltage ◽  
Saturation Region ◽  
Linear Differential ◽  
Low Supply Voltage

This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR

2009 ◽  
Vol 18 (03) ◽  
pp. 519-534 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Mos Transistor ◽  
Curvature Correction ◽  
Current Consumption ◽  
Correction Technique

Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

Effective Circuit Design Methodologies for Standby Leakage Power Reduction

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Model Parameters ◽  
Mos Transistor ◽  
Design Methodologies ◽  
Transistor Model

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).

scholarly journals High-Precision Current Conveyor based on BDQFG Miller Ota

2019 ◽  
Vol 8 (2) ◽  
pp. 823-826
Keyword(s):  
Frequency Response ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Floating Gate ◽  
High Current ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier ◽  
High Bandwidth ◽  
Low Supply Voltage

The paper presents a sub-volt design of highly precise second-generation current conveyor (CCII  ) using Miller compensated Operational Transconductance Amplifier (OTA) designed using bulk driven quasi-floating gate (BDQFG) MOSFET. The bulk-driven approach help in working of proposed CCII  at low supply voltage. Moreover, followed BDQFG technique results in improves the transconductance and frequency response of the circuit over standalone bulk-driven technique. The proposed CCII  operates at  0.4V. Other performances which encourage its wide applicability are in terms of high current range and high bandwidth. The analysis of proposed current conveyor is carried in 0.18 m twin-well CMOS technology using HSpice

scholarly journals A New Current-Shaping Technique Based on a Feedback Injection Mechanism to Reduce VCO Phase Noise

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6583
Author(s):  
Francisco Javier del Pino Suárez ◽  
Sunil Lalchand Khemchandani
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Chip Area ◽  
Load Variations ◽  
Voltage Controlled Oscillators ◽  
Radar Sensors ◽  
Low Area ◽  
Injection Mechanism

Inductor-capacitor voltage controlled oscillators (LC-VCOs) are the most common type of oscillator used in sensors systems, such as transceivers for wireless sensor networks (WSNs), VCO-based reading circuits, VCO-based radar sensors, etc. This work presents a technique to reduce the LC-VCOs phase noise using a new current-shaping method based on a feedback injection mechanism with only two additional transistors. This technique consists of keeping the negative resistance seen from LC tank constant throughout the oscillation cycle, achieving a significant phase noise reduction with a very low area increase. To test this method an LC-VCO was designed, fabricated and measured on a wafer using 90 nm CMOS technology with 1.2 V supply voltage. The oscillator outputs were buffered using source followers to provide additional isolation from load variations and to boost the output power. The tank was tuned to 1.8 GHz, comprising two 1.15 nH with 1.5 turns inductors with a quality factor (Q) of 14, a 3.27 pF metal-oxide-metal capacitor, and two varactors. The measured phase noise was −112 dBc/Hz at 1 MHz offset. Including the pads, the chip area is 750 × 850 μm2.

A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient

2019 ◽  
Vol 28 (07) ◽  
pp. 1950120 ◽  
Author(s):  
R. Nagulapalli ◽  
K. Hayatleh ◽  
S. Barker ◽  
A. A. Tammam ◽  
P. Georgiou ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Absolute Temperature ◽  
Threshold Region ◽  
Bandgap Reference ◽  
Na Current ◽  
Mos Transistor ◽  
Self Bias

This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[Formula: see text]V, and generates a 286[Formula: see text]mV reference voltage with a temperature coefficient of 59[Formula: see text]ppm/∘C. The circuit takes 413[Formula: see text]nA current from 0.55[Formula: see text]V supply and occupies 0.00986[Formula: see text]mm2 of active area.

Design of a Low-Phase-Noise LC Voltage Controlled Oscillator

2014 ◽  
Vol 519-520 ◽  
pp. 1095-1098
Author(s):  
Cheng Hong Dong ◽  
Chang Chun Zhang ◽  
Yu Feng Guo ◽  
Lei Lei Liu ◽  
Xin Cun Ji ◽  
...  
Keyword(s):  
Phase Noise ◽  
Figure Of Merit ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Voltage Controlled Oscillator ◽  
Frequency Range ◽  
Supply Current ◽  
Low Phase Noise ◽  
Lc Vco

A novel low phase noise LC Voltage Controlled Oscillator (LC-VCO) is designed in standard 0.18μm CMOS technology. Instead of common NMOS cross-pairs for a conventional complementary LC VCO, both body-biasing and Q-enhancement techniques are employed to provide a larger negative resistance for the VCO. Post-layout simulations showed that it can oscillate at a frequency range of 4.34-4.73GHz, and comsume a supply current of 1.52mA from a supply voltage of 1.8V. The VCO achieves a phase noise of -132.8dBc/Hz @ 1MHz offset and a figure of merit (FOM) of -195.9dBc/Hz at the frequency of 4.5GHz. A die area of 475μm×498.6μm is occupied.

scholarly journals An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Radar Sensor ◽  
Frequency Locking ◽  
Current Reuse ◽  
Sensor Applications ◽  
Locking Range

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

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