LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR

2009 ◽  
Vol 18 (03) ◽  
pp. 519-534 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Mos Transistor ◽  
Curvature Correction ◽  
Current Consumption ◽  
Correction Technique

Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

scholarly journals A curvature-corrected CMOS bandgap reference

2005 ◽  
Vol 1 ◽  
pp. 181-184
Author(s):  
O. Mitrea ◽  
C. Popa ◽  
A. M. Manolescu ◽  
M. Glesner
Keyword(s):  
Power Consumption ◽  
Cmos Technology ◽  
Measured Temperature ◽  
Bandgap Reference ◽  
Voltage Reference ◽  
Weak Inversion ◽  
Chip Area ◽  
Curvature Correction ◽  
Small Correction ◽  
Correction Technique

Abstract. This paper presents a CMOS bandgap reference that employs a curvature correction technique for compensating the nonlinear voltage temperature dependence of a diode connected BJT. The proposed circuit cancels the first and the second order terms in the VBE(T ) expansion by using the current of an autopolarizedWidlar source and a small correction current generated by a MOSFET biased in weak inversion. The voltage reference has been fabricated in a 0.35µm 3Metal/2Poly CMOS technology and the chip area is approximately 70µm × 110µm. The measured temperature coefficient is about 10.5 ppm/K over a temperature range of 10– 90°C while the power consumption is less than 1.4mW.

NEGATIVE RESISTANCE ACTIVE RESISTOR WITH IMPROVED LINEARITY AND FREQUENCY RESPONSE

2009 ◽  
Vol 18 (01) ◽  
pp. 1-10 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Frequency Response ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Original Method ◽  
Order Effects ◽  
Mos Transistors ◽  
Mos Transistor ◽  
Saturation Region ◽  
Linear Differential

An original active resistor circuit will be presented. The main advantages of the new proposed implementations are the improved linearity, small area consumption and improved frequency response. An original technique for linearizing the I(V) characteristic of the active resistor will be proposed, based on the utilization of a new linear differential amplifier, and on a current-pass circuit. The linearization of the original differential structure is achieved by compensating the quadratic characteristic of the MOS transistor operating in the saturation region by an original square-root circuit. The errors introduced by the second-order effects will be strongly reduced, while the circuit frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. In order to design a circuit having a negative equivalent resistance, an original method specific to the proposed implementation of the active resistor circuit will be presented. The circuit is implemented in 0.35 μm CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (± 500 mV) and a small value of the supply voltage (± 3 V).

A High Temperature 4H-SiC Voltage Reference for Depletion Mode GaN-Based Circuits

2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000118-000121
Author(s):  
ZiHao Zhang ◽  
Jebreel M. Salem ◽  
Dong Sam Ha
Keyword(s):  
High Temperature ◽  
High Temperatures ◽  
Oil And Gas ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Voltage Range ◽  
Oil And Gas Exploration ◽  
Low Leakage ◽  
Temperature Applications

Abstract High temperature electronics are highly demanded for many applications such as automotive, space, and oil and gas exploration. Electronic circuits for those applications are required to operate reliably without using bulky cooling systems. Circuits based on silicon (Si) suffer from high leakage currents at high temperatures. Silicon Carbide (SiC) circuits, on the other hand, are suitable for high temperature applications due to the wide bandgap and offer high breakdown voltage and low leakage current. This paper presents a negative voltage reference for high temperature applications using commercial-off-the-shelf (COTS) 4H-SiC transistors. The proposed voltage reference adopts Widlar bandgap reference topology, and it aims to provide a negative reference voltage for Gallium Nitride (GaN) circuits operating at high temperatures. Measurement results indicate that the proposed circuit provides a negative reference voltage with a low temperature coefficient of 42 ppm/°C for temperatures ranging from 25 °C to 250 °C. The proposed circuit also operates reliably for a wide supply voltage range of −7.5 V to −15 V for the temperature range.

scholarly journals Low-Power CMOS Integrated Hall Switch Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Rongshan Wei ◽  
Shizhong Guo ◽  
Shanzhi Yang
Keyword(s):  
Supply Voltage ◽  
Reducing Power ◽  
Cmos Technology ◽  
Sleep Mode ◽  
Test Results ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Power Cmos ◽  
Switch Circuit ◽  
Hall Element

This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA.

Effective Circuit Design Methodologies for Standby Leakage Power Reduction

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Model Parameters ◽  
Mos Transistor ◽  
Design Methodologies ◽  
Transistor Model

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).

A High-Order Curvature-Compensated Bandgap Voltage Reference for Micro-Gyroscope

2012 ◽  
Vol 503 ◽  
pp. 12-17
Author(s):  
Qiang Li ◽  
Xiao Yun Tan ◽  
Guan Shi Wang
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Bandgap Reference ◽  
Voltage Reference ◽  
Temperature Dependent ◽  
Power Supply Voltage ◽  
Gyroscope System ◽  
Bandgap Voltage Reference ◽  
Reference Circuit

The reference is an important part of the micro-gyroscope system. The precision and stability of the reference directly affect the precision of the micro-gyroscope. Unlike the traditional bandgap reference circuit, a circuit using a temperature-dependent resistor ratio generated by a highly-resistive poly resistor and a diffusion resistor in CMOS technology is proposed in this paper. The complexity of the circuit is greatly reduced. Implemented with the standard 0.5μm CMOS technology and 9V power supply voltage, in the range of -40~120°C, the temperature coefficient of the proposed bandgap voltage reference can achieve to about 1.6 ppm/°C. The PSRR of the circuit is -107dB.

A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-Capacitor Bandgap Voltage Reference

2020 ◽  
pp. 2150029
Author(s):  
Emad Ebrahimi ◽  
Maliheh Arabnasery
Keyword(s):  
Process Variations ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Reference ◽  
Op Amp ◽  
Offset Voltage ◽  
Bandgap Voltage Reference

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

scholarly journals A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift

2018 ◽  
Vol 27 (08) ◽  
pp. 1850128 ◽  
Author(s):  
R. Nagulapalli ◽  
K. Hayatleh ◽  
Steve Barker ◽  
Sumathi Raparthy ◽  
Nabil Yassine ◽  
...  
Keyword(s):  
Power Supply ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Temperature Drift ◽  
Ultra Low Power

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65[Formula: see text]nm CMOS has been developed and occupies 0.0039[Formula: see text]mm2, and at room temperature, it generates a 204[Formula: see text]mV reference voltage with 1.3[Formula: see text]mV drift over a wide temperature range (from [Formula: see text]40[Formula: see text]C to 125[Formula: see text]C). This has been designed to operate with a power supply voltage down to 0.6[Formula: see text]V and consumes 1.8[Formula: see text]uA current from the supply. The simulated temperature coefficient is 40[Formula: see text]ppm/[Formula: see text]C.

scholarly journals A 167.18 ppm/°C temperature coefficient, area efficient voltage reference using only MOS transistors

2020 ◽  
Vol 17 (1) ◽  
pp. 31-40
Author(s):  
Guru Prasad ◽  
Kumara Shama
Keyword(s):  
Temperature Coefficient ◽  
Room Temperature ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Inversion Region ◽  
Strong Inversion ◽  
Reference Circuit ◽  
Simulation Results

In this paper, design of a voltage reference circuit using only MOS transistors and without employing an operational amplifier is presented. A proportional to absolute temperature [PTAT] voltage and a PTAT current are designed then difference of the PTAT voltage and product of the PTAT current and resistor gives the temperature independent voltage. The advantages of both sub-threshold and strong inversion region operation of MOS transistors are exploited in the design. The voltage reference is implemented using standard CMOS 180 nm technology. The voltage reference provides a voltage of 224.3 mV consuming a quiescent current of 30 ?A at room temperature. Post layout simulation results show that the proposed voltage reference has a temperature coefficient of 167.18 ppm/?C and varies only 3mV when there is a ?10% variation in supply voltage. The circuit occupies an area of only 93.6?32.6?m on the chip, making it suitable for area constraint applications.

РАЗРАБОТКА И ИССЛЕДОВАНИЕ СВЕТОДИОДНОГО ДРАЙВЕРА

2020 ◽  
Vol 96 (3s) ◽  
pp. 631-634
Author(s):  
О.Л. Климов ◽  
С.М. Игнатьев ◽  
И.В. Ермаков
Keyword(s):  
Research And Development ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Output Current ◽  
Led Driver ◽  
Voltage Range ◽  
Temperature Range ◽  
Current Consumption ◽  
Current Error

Представлены результаты разработки и исследования светодиодного драйвера в КМОП-технологии уровня 0,6 мкм. Погрешность выходного тока драйвера с учетом технологического разброса в диапазоне напряжений питания от 4 до 20 В и диапазоне температур от -60 до +125 °С составила менее ±5 % от номинального значения 3,55 мА. Ток потребления драйвера - менее 100 мкА, а занимаемая площадь - 0,3 х 0,3 мм2. The paper presents the research and development of the LED driver in 0.6 μm CMOS technology. When the supply voltage range is from 4 to 20 V and temperature range is from -60 to +125 °C the output current error of the LED driver taking into account the process corners is less than ±5 % of the nominal value 3.55 mA. The LED driver current consumption is less than 100 uA and the area is less than 0.3 х 0.3 mm2.

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