Application of Advanced Back-Side Optical Techniques in ASICs

2013 ◽  
Vol 21 (3) ◽  
pp. 30-35
Author(s):  
Douglas Martin ◽  
Samuel Beilin ◽  
Brett Hamilton ◽  
Darin York ◽  
Philip Baker ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Photon Emission ◽  
Back Side ◽  
Voltage Imaging ◽  
Root Cause ◽  
Silicon Transistors ◽  
Cause Of Failure ◽  
Metal Interconnects ◽  
Application Specific

Failure analysis is important in determining root cause for appropriate corrective action. In order to perform failure analysis of microelectronic application-specific integrated circuits (ASICs) delidding the device is often required. However, determining root cause from the front side is not always possible due to shadowing effects caused by the ASIC metal interconnects. Therefore, back-side polishing is used to reveal an unobstructed view of the ASIC silicon transistors. This paper details how back-side polishing in conjunction with laser-scanned imaging (LSI), laser voltage imaging (LVI), laser voltage probing (LVP), photon emission microscopy (PEM), and laser-assisted device alterations (LADA) were used to uncover the root cause of failure of two ASICs.

Diffractive Lenses for High Resolution Laser Based Failure Analysis

2005 ◽  
Author(s):  
Frank Zachariasse ◽  
Martijn J. Goossens
Keyword(s):  
High Resolution ◽  
Failure Analysis ◽  
Laser Scanning ◽  
New Method ◽  
Lateral Resolution ◽  
Back Side ◽  
Diffractive Lens ◽  
Standard Equipment ◽  
Diffractive Lenses ◽  
Better Than

Abstract In this paper we present a new method to increase the lateral resolution available in laser scanning failure analysis tools. By fabricating a diffractive lens on the back side of the die, the area of the circuit of interest, directly underneath the lens, may be studied with a lateral resolution up to 3.5 times better than without the lens. This method is easily implemented with standard equipment already present in most failure analysis laboratories, and overcomes some significant problems encountered with alternative resolution enhancing schemes.

Scanning Optical Microscopy Application in Micron® Memory Devices

2005 ◽  
Author(s):  
Wong Yaw Yuan ◽  
T.L. Edmund Poh ◽  
David Lam
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Memory Devices ◽  
Back Side ◽  
Induced Voltage ◽  
Scanning Optical Microscopy ◽  
Side Emission ◽  
Complex Circuits

Abstract The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.

Pulse Laser Ablation Techniques for IC Package Substrate Modifications and Validation

2016 ◽  
Author(s):  
Matthew M. Mulholland ◽  
Ahmed A. Helmy ◽  
Anthony V. Dao
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Pulse Laser ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Front Side ◽  
Local Approach ◽  
Ic Package ◽  
Level Analysis

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

Failure Analysis from the Backside of a Die

2000 ◽  
Author(s):  
Silke Liebert
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Gate Oxide ◽  
Physical Analysis ◽  
Back Side ◽  
Bulk Silicon ◽  
Analysis Methods ◽  
On Chip ◽  
Voltage Contrast ◽  
Side Flow

Abstract A back side failure analysis flow has been developed in order to enable failure analysis of flip-chip, lead-on-chip dies and within multi-metal-level dies. A combination with frontside failure analysis methods is possible too. The back side flow consists of stepwise bulk silicon removal, electrical and physical failure analysis methods. Four different methods for bulk silicon thinning in order to localize electrical defects using PEM are compared. A method to remove the bulk silicon after PEM analysis to expose the gate oxide level of a die has been developed. Different back side applications like physical analysis of gate oxide defects, passive voltage contrast and microprobing with an AFM tip for detection of interrupts within conductive interconnects are described.

Non-Invasive Backside Failure Analysis of Integrated Circuits by Time-Dependent Light Emission: Picosecond Imaging Circuit Analysis

1998 ◽  
Author(s):  
J.A. Kash ◽  
J.C. Tsang ◽  
D.R. Knebel ◽  
D.P. Vallett
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Parallel Imaging ◽  
Light Emission ◽  
Logic Gate ◽  
Circuit Analysis ◽  
Back Side ◽  
Emission Data ◽  
Time Resolved ◽  
Non Invasive

Abstract A noninvasive backside probe of integrated circuits has been developed. This new probe can diagnose at-speed failures, stuck faults, and other defects. Because it is a highly parallel imaging technique, faults may be isolated which are difficult to locate by other methods. This optical technique has been named “PICA”, for picosecond imaging circuit analysis. PICA relies on the fact that an FET in a CMOS circuit emits a picosecond pulse of light each time the logic gate changes state. The source of this emission is explained. The PICA technique, which combines optical imaging of the emission with picosecond time-resolution, is described. Because of the imaging, time-resolved emission data is acquired for many transistors in parallel. The use of the emission for failure analysis and AC characterization of integrated circuits is demonstrated. Because the emission can be detected from either the front or back side of the chip, it can be used for both front and back side analysis.

Back side emission microscopy for failure analysis

1996 ◽  
Author(s):  
Nevil M. Wu ◽  
Kenneth Tang ◽  
James H. Lin
Keyword(s):  
Failure Analysis ◽  
Back Side ◽  
Emission Microscopy ◽  
Side Emission

Guideline for Interpreting IR Laser Stimulation Signal on Semiconductors for Materials and for Improving Failure Analysis Flow

2005 ◽  
Author(s):  
A. Firiti ◽  
G. Haller ◽  
F. Beaudoin ◽  
P. Perdu ◽  
D. Lewis ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Turnaround Time ◽  
Physical Analysis ◽  
Substrate Thickness ◽  
Back Side ◽  
Metallic Materials ◽  
Laser Stimulation ◽  
Ir Laser ◽  
Silicon Thickness ◽  
The Ideal

Abstract Infra-red Thermal Laser Stimulation (TLS) signatures obtained on semiconductor materials can be difficult to interpret and to distinguish from signatures from metallic materials. Investigations presented here consist in the study of TLS signals on unsilicided/silicided polycrystalline and diffused silicon resistors of 0.18µm technology. The influence of each process parameter on the TLS signal has been observed and evaluated from the front and back side of the circuit. This allowed us to quantify the effect of the silicon substrate thickness on TLS signal detection and to determine the ideal silicon thickness for sample preparation. This study also completes our methodology based on the TCR parameter which aims at improving defect localization in the depth (Z) of circuitry. As it will be shown through failure analysis case studies, this methodology increases the physical analysis success rate and reduces the turnaround time.

Failure Analysis From Back Side of Die

1996 ◽  
Author(s):  
N.M. Wu ◽  
K. Weaver ◽  
J.H. Lin
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Back Side ◽  
Induced Current ◽  
Front Side ◽  
Root Cause ◽  
Isolation Techniques ◽  
Cause Of Failure ◽  
Emission Microscopy ◽  
Side Emission

Abstract With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.

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