Application of Advanced Back-Side Optical Techniques in ASICs

2013 ◽  
Vol 21 (3) ◽  
pp. 30-35
Author(s):  
Douglas Martin ◽  
Samuel Beilin ◽  
Brett Hamilton ◽  
Darin York ◽  
Philip Baker ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Photon Emission ◽  
Back Side ◽  
Voltage Imaging ◽  
Root Cause ◽  
Silicon Transistors ◽  
Cause Of Failure ◽  
Metal Interconnects ◽  
Application Specific

Failure analysis is important in determining root cause for appropriate corrective action. In order to perform failure analysis of microelectronic application-specific integrated circuits (ASICs) delidding the device is often required. However, determining root cause from the front side is not always possible due to shadowing effects caused by the ASIC metal interconnects. Therefore, back-side polishing is used to reveal an unobstructed view of the ASIC silicon transistors. This paper details how back-side polishing in conjunction with laser-scanned imaging (LSI), laser voltage imaging (LVI), laser voltage probing (LVP), photon emission microscopy (PEM), and laser-assisted device alterations (LADA) were used to uncover the root cause of failure of two ASICs.

Failure Analysis From Back Side of Die

1996 ◽  
Author(s):  
N.M. Wu ◽  
K. Weaver ◽  
J.H. Lin
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Back Side ◽  
Induced Current ◽  
Front Side ◽  
Root Cause ◽  
Isolation Techniques ◽  
Cause Of Failure ◽  
Emission Microscopy ◽  
Side Emission

Abstract With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.

Introduction of Spectral Mapping through Transmission Grating, Derivative Technique of Photon Emission

2014 ◽  
Author(s):  
Thierry Parrassin ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
Hervé Deslandes
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Light Emission ◽  
Photon Emission ◽  
Optical Path ◽  
Spectral Mapping ◽  
Additional Information ◽  
Transmission Grating ◽  
Emission System ◽  
Advance Knowledge

Abstract By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.

Novel FIB Use for Failure Analysis of MEMS Gyroscopes

2016 ◽  
Author(s):  
Nathan Wang ◽  
Saunil Shah ◽  
Camille Garcia ◽  
Vicente Pasating ◽  
George Perreault
Keyword(s):  
Thin Films ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
New Techniques ◽  
Unique Challenge ◽  
Root Cause ◽  
Large Size ◽  
Mems Gyroscopes

Abstract MEMS samples, with their relatively large size and weight, present a unique challenge to the failure analyst as they also included thin films and microstructures used in conventional integrated circuits. This paper describes how to accommodate the large MEMS structures without skimping on the microanalyses needed to get to the root cause. Investigations of tuning folk gyroscopes were used to demonstrate these new techniques.

Case Study—Failure Analysis of a Multiplexer

2016 ◽  
Author(s):  
Michael Woo ◽  
Marcos Campos ◽  
Luigi Aranda
Keyword(s):  
Failure Analysis ◽  
High Reliability ◽  
Component Failure ◽  
Root Cause ◽  
Knowing That ◽  
Cause Of Failure ◽  
The Cost

Abstract A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.

Reliability Estimation and Failure Analysis of Multilayer Ceramic Chip Capacitors

2003 ◽  
Vol 17 (08n09) ◽  
pp. 1318-1323 ◽  
Author(s):  
Seok Jun Yang ◽  
Jin Woo Kim ◽  
Dong Su Ryu ◽  
Myung Soo Kim ◽  
Joong Soon Jang
Keyword(s):  
Failure Analysis ◽  
Life Stress ◽  
Control Unit ◽  
Accelerated Life Testing ◽  
Reliability Estimation ◽  
Accelerated Life Test ◽  
Root Cause ◽  
Accelerated Life ◽  
Cause Of Failure ◽  
Multilayer Ceramic

This paper presents the failure analysis and the reliability estimation of a multilayer ceramic chip capacitor. For the failed samples used in an automobile engine control unit, failure analysis was made to identify the root cause of failure and it was shown that the migration and the avalanche breakdown were the dominant failure mechanisms. Next, an accelerated life testing was designed to estimate the life of the MLCC. It is assumed that Weibull lifetime distribution and the life-stress relationship proposed Prokopowicz and Vaskas. The life-stress relationship and the acceleration factor are estimated by analyzing the accelerated life test data.

Metallurgy Selection of Tubing in Sucker Rod Pump Wells Plagued with Pitting and Abrasion Issues

2021 ◽  
Author(s):  
Rishabh Uniyal ◽  
Rajeev Bansal ◽  
Suman Kumar Jaruhar ◽  
Sudipta Biswas ◽  
Sagun Devshali ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Primary Objective ◽  
General Corrosion ◽  
Uniform Corrosion ◽  
Mechanical Wear ◽  
Root Cause ◽  
Sucker Rod ◽  
Sucker Rod Pump ◽  
Cause Of Failure ◽  
Corrosion Pitting

Abstract Analysis of tubing failure of SRP wells with respect to uniform corrosion, pitting and mechanical abrasion has been carried out. The primary objective includes the identification of root cause of failure and suggesting alternate metallurgy. Many wells in an onshore field in ONGC were facing the acute problem of general corrosion, pitting and rod-tubing wear. The methodology for carrying out the study consists of a Failure Analysis of a retrieved sample of the failed tubing from one of the affected wells. This included a thorough visual inspection, Scanning Electron Microscope analysis and X-Ray Diffraction analysis. The results of these tests were backed up by software simulation in Honeywell Predict. Metallurgy selection involved multiple exhaustive simulation runs in Honeywell Software Socrates which was corroborated by relevant oilfield standards as well as literature available on the subject matter. Based on the failure analysis and simulation runs, it was concluded that besides the issue of uniform corrosion and pitting, many of the affected wells are also facing the problem of tubing failures due to abrasion and mechanical wear. It is pertinent to note that the major contributor of the frequent tubing failures in the candidate wells selected for the study were pitting and corrosion. Nevertheless, Abrasion always remains a key threat to the tubing string integrity in rod-pump wells. Therefore, the existing tubing metallurgy of N-80 grade Carbon Steel was deemed inadequate in the absence of reliable corrosion inhibitor continuous dosing facilities. A tubing metallurgy that takes care of both pitting corrosion as well as abrasion and mechanical wear was sought. UNS 41426/41427 or the modified version of 13 Chrome, commercia lly known as Super Martensitic 13 Chrome, are available in 95 ksi and 110 ksi grades. These grades have a maximum hardness of 28-32 HRC which is substantially high compared to L-80 13 Cr (maximum 23 HRC). Also, as this alloy has 4-6% Nickel, it provides added protection against uniform corrosion as well as pitting and hence was recommended. The paper specifically analyses tubing failure in Sucker rod-pump wells due to corrosion, pitting and abrasion. After exploring various viable options, adequate tubing metallurgy has been recommended that should take care of corrosion, pitting as well as mechanical wear problems.

scholarly journals Die Backside FIB Preparation for Identification and Characterization of Metal Voids

1999 ◽  
Author(s):  
Ann N. Campbell ◽  
William F. Filter ◽  
Nicholas Antoniou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Milling Process ◽  
Plan View ◽  
Metal Interconnects

Abstract Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

Engineering Design Process Investigation in a Failure Analysis

2021 ◽  
pp. 20-29
Author(s):  
Steven Kushnick
Keyword(s):  
Failure Analysis ◽  
Engineering Design ◽  
Design Process ◽  
Failure Modes ◽  
Process Information ◽  
Root Cause ◽  
Management Actions ◽  
Engineering Design Process ◽  
Mode Of Failure ◽  
Cause Of Failure

Abstract The intent of this article is to assist the failure analyst in understanding the underlying engineering design process embodied in a failed component or system. It begins with a description of the mode of failure. This is followed by a section providing information on the root cause of failure. Next, the article discusses the steps involved in the engineering design process and explains the importance of considering the engineering design process. Information on failure modes and effects analysis is also provided. The article ends with a discussion on the consequence of management actions on failures.

MBIST Driven SRAM Failure Analysis Using Laser Voltage Imaging and Laser Voltage Probing

2019 ◽  
Author(s):  
Jessica Yang ◽  
Omprakash Rengaraj ◽  
Puneet Gupta ◽  
Rudolf Schlangen
Keyword(s):  
Failure Analysis ◽  
Photon Emission ◽  
Random Access ◽  
Random Access Memory ◽  
Fault Isolation ◽  
Static Random Access Memory ◽  
Production Testing ◽  
Access Memory ◽  
Electrical Failure ◽  
Voltage Imaging

Abstract Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

Pulse Laser Ablation Techniques for IC Package Substrate Modifications and Validation

2016 ◽  
Author(s):  
Matthew M. Mulholland ◽  
Ahmed A. Helmy ◽  
Anthony V. Dao
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Pulse Laser ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Front Side ◽  
Local Approach ◽  
Ic Package ◽  
Level Analysis

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

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