Pulse Laser Ablation Techniques for IC Package Substrate Modifications and Validation

2016 ◽  
Author(s):  
Matthew M. Mulholland ◽  
Ahmed A. Helmy ◽  
Anthony V. Dao
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Pulse Laser ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Front Side ◽  
Local Approach ◽  
Ic Package ◽  
Level Analysis

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

A Combination Continuous Wave and Pulse Laser Assisted Chemical Etching Processes through Encapsulated IC Packaging

2015 ◽  
Author(s):  
Matthew M. Mulholland ◽  
Scott Silverman
Keyword(s):  
Integrated Circuits ◽  
Pulse Laser ◽  
Chemical Etching ◽  
Focused Ion Beam ◽  
Continuous Wave ◽  
Ion Beam ◽  
Packaging Materials ◽  
Local Approach ◽  
Solder Bumps ◽  
Ic Packaging

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require backside sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces will typically use conventional Laser Chemical Etching (LCE) platforms. The focus of this analysis will be to investigate and conjoin previously published techniques to this local preparation by using a combination of laser sources. A Continuous Wave (CW) and Pulse laser will be used at various processing stages to de-process IC packaging materials silicon and mold compound encapsulation.

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

Direct Imaging of Device Characteristics In a Focused ion Beam System

1998 ◽  
Vol 4 (S2) ◽  
pp. 652-653 ◽  
Author(s):  
A. N. Campbell ◽  
J. M. Soden
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Material Removal ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Yield Enhancement ◽  
The Past ◽  
Design Changes ◽  
Design Debugging

A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

A Transmission X-ray Microscope (TXM) for Non-destructive 3D Imaging of ICs at Sub-100 nm Resolution

2002 ◽  
Author(s):  
Steve Wang ◽  
Frederick Duewer ◽  
Shashidar Kamath ◽  
Christopher Kelly ◽  
Alan Lyon ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Process Development ◽  
Imaging System ◽  
Ion Beam ◽  
Layer By Layer ◽  
X Ray ◽  
Submicron Structures

Abstract Xradia has developed a laboratory table-top transmission x-ray microscope, TXM 54-80, that uses 5.4 keV x-ray radiation to nondestructively image buried submicron structures in integrated circuits with at better than 80 nm 2D resolution. With an integrated tomographic imaging system, a series of x-ray projections through a full IC stack, which may include tens of micrometers of silicon substrate and several layers of Cu interconnects, can be collected and reconstructed to produce a 3D image of the IC structure at 100 nm resolution, thereby allowing the user to detect, localize, and characterize buried defects without having to conduct layer by layer deprocessing and inspection that are typical of conventional destructive failure analysis. In addition to being a powerful tool for both failure analysis and IC process development, the TXM may also facilitate or supplant investigations using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and focused ion beam (FIB) tools, which generally require destructive sample preparation and a vacuum environment.

FIB Micro-Surgery on Flip-Chips from the Backside

1998 ◽  
Author(s):  
Raymond Lee ◽  
Nicholas Antoniou
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Bulk Silicon ◽  
Front Side ◽  
Large Hole ◽  
Area Of Interest ◽  
Flip Chip Packaging ◽  
Micro Surgery

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.

A Method to Enhance the Front-Side Lapping Process for Localisation of Sub-Surface Defect for Advanced Packages

2018 ◽  
Author(s):  
Sze Yee Tan ◽  
Chiu Soon Wong ◽  
Chea Wee Lo ◽  
Cin Sheng Goh
Keyword(s):  
Failure Analysis ◽  
Surface Defect ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Assembly Process ◽  
Front Side ◽  
Root Cause ◽  
The Common ◽  
Thinning Process ◽  
Non Destructive

Abstract In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.

scholarly journals Die Backside FIB Preparation for Identification and Characterization of Metal Voids

1999 ◽  
Author(s):  
Ann N. Campbell ◽  
William F. Filter ◽  
Nicholas Antoniou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Milling Process ◽  
Plan View ◽  
Metal Interconnects

Abstract Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

scholarly journals A Quantitative Method for Measuring Remaining Silicon Thickness during XeF2 FIB Trenching for Backside Circuit Operations

2017 ◽  
Author(s):  
G.P. Salazar ◽  
R.J. Shul ◽  
S.N. Ball ◽  
M.J. Rye ◽  
B.S. Phillips ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Silicon Substrate ◽  
Quantitative Method ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Quantitative Measure ◽  
Mechanical Methods ◽  
Silicon Thickness

Abstract Backside circuit edit (CE) remains a crucial failure analysis (FA) capability, enabling design modifications on advanced integrated circuits. [1-9] A key requirement of this activity is to approach the active transistor layer of the silicon through the removal of the silicon substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques (continuous or pulsed), or chemical assisted focused ion beam (FIB) etching to accomplish the thinning. Each of these methods presents different strengths and weaknesses, from their reliability to complexity, but very few techniques provide a precise and accurate quantitative measure of the remaining silicon thickness (RST). Here, we will discuss the use of a FIB with XeF2 for backside Si removal, and the development of an in-situ, accurate measurement of RST.

Turning Sample Into (Re)Solution—Focused Ion Beam Shaped Solid Immersion Lenses

2015 ◽  
Author(s):  
Philipp Scholz ◽  
Michael Sadowski ◽  
Christian Boit ◽  
Sebastian Kupijai ◽  
Marvin Henniges ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Photonic Integrated Circuits ◽  
Ion Beam ◽  
Signal Transmission ◽  
Optical Signal ◽  
Analysis Process ◽  
First Case ◽  
Solution Focused

Abstract This work is a unique solution for enhancing optical failure analysis and optical signal transmission. Optical failure analysis remains to be a vital part of the analysis process, despite shrinking feature sizes and challenging package technologies. The presented optical signal transmission supports the development of photonic integrated circuits. The key component is a Focused Ion Beam (FIB) process which shapes optical lenses out of the sample material leading to an improvement in lateral resolution and signal transmission. Two cases are shown that demonstrate these improvements. The first case is an optical backside analysis in a spatially confined opening of a package where other Solid Immersion Lens (SIL) systems could not be applied. It offers an improvement in spatial resolution by a factor of 2, down to a FWHM of 387 nm. The second case is a novel application for FIB shaped lenses aiming at photonic integrated circuits. This lens is created out of the isolating frontside and improves the grating coupler efficiency by a factor of 4.1.

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