Scanning Optical Microscopy Application in Micron® Memory Devices

2005 ◽  
Author(s):  
Wong Yaw Yuan ◽  
T.L. Edmund Poh ◽  
David Lam
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Memory Devices ◽  
Back Side ◽  
Induced Voltage ◽  
Scanning Optical Microscopy ◽  
Side Emission ◽  
Complex Circuits

Abstract The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.

Failure Analysis From Back Side of Die

1996 ◽  
Author(s):  
N.M. Wu ◽  
K. Weaver ◽  
J.H. Lin
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Back Side ◽  
Induced Current ◽  
Front Side ◽  
Root Cause ◽  
Isolation Techniques ◽  
Cause Of Failure ◽  
Emission Microscopy ◽  
Side Emission

Abstract With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

Techniques for Localization of IC Interconnection Defects

2002 ◽  
Vol 716 ◽  
Author(s):  
Edward I. Cole
Keyword(s):  
Integrated Circuit ◽  
Constant Current ◽  
Induced Voltage ◽  
Contrast Imaging ◽  
Thermally Induced ◽  
Imaging Results ◽  
Starting Point ◽  
Site Localization ◽  
Scanning Optical Microscopy ◽  
Failure Site

AbstractThe advances in integrated circuit technology has made failure site localization extremely challenging. Charge-Induced Voltage Alteration (CIVA), Low Energy CIVA (LECIVA), Light-Induced Voltage Alteration (LIVA), Seebeck Effect Imaging (SEI) and Thermally-Induced Voltage Alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy (SEM) techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects. In addition to the techniques listed above, the Resistive Contrast Imaging (RCI) for localizing opens on metal test patterns will be described as a starting point for the “IVA” technologies.

Near-Field Scanning Optical Microscopy for Through-Silicon Imaging and Fault Isolation of Integrated Circuits

2014 ◽  
Author(s):  
R. Giridharagopal ◽  
T.M. Eiles ◽  
B. Niu
Keyword(s):  
Optical Microscopy ◽  
Integrated Circuit ◽  
Near Field ◽  
Diffraction Limit ◽  
Fault Isolation ◽  
Lateral Resolution ◽  
Excitation Wavelength ◽  
Process Technology ◽  
Scanning Optical Microscopy ◽  
Near Field Scanning

Abstract We present the first known images acquired using near-field scanning optical microscopy (NSOM) through backside silicon on functional integrated circuit samples with higher resolution than conventional fault isolation (FI) tools. NSOM offers the possibility of substantially-improved lateral resolution independent of excitation wavelength. Current FI techniques have challenged the resolution limits of conventional optics technology, even in the best solid immersion lens (SIL) to date. This poses a problem for future process technology nodes. This resolution barrier is a by-product of the diffraction limit. In Fourier terms, a conventional lens filters out highfrequency information and thus limits the resolution. In NSOM, by placing a tip with an aperture in extreme proximity to the surface it is possible to capture the near-field light that contains high-frequency information, thereby circumventing the diffraction limit. The tangible benefit is that the resolution is substantially improved. We show that NSOM can be used in backside subsurface imaging of silicon, mirroring the paradigm used in typical optical FI. We present optical reflectance data through ~100 nm of remaining backside Si on functional 22 nm CMOS IC parts with lateral resolution approaching 100 nm. We then discuss potential methods for using NSOM in practical backside fault isolation applications and for improving signal-to-noise ratio (SNR).

Non-Destructive 3D Failure Analysis Work Flow for Electrical Failure Analysis in Complex 2.5D-Based Devices Combining 3D Magnetic Field Imaging and 3D X-Ray Microscopy

2018 ◽  
Author(s):  
Antonio Orozco ◽  
Elena Talanova ◽  
Alex Jeffers ◽  
Florencia Rusli ◽  
Bernice Zee ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
X Ray ◽  
Electrical Failure ◽  
Magnetic Field Imaging ◽  
3D Stacking ◽  
Field Imaging

Abstract Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Moore”). This complex 3D geometry, with an abundance of opaque layers and interconnects, presents a great challenge for failure analysis (FA). Three-dimensional (3D) magnetic field imaging (MFI) has proven to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allows for submicron vertical resolution. 3D X-ray microscopy (XRM) enables 3D tomographic imaging of advanced IC packages without the need to destroy the device. This is because it employs both geometric and optical image magnifications to achieve high spatial resolution. In this paper, we propose a fully nondestructive, 3D-capable workflow for FA comprising 3D MFI and 3D XRM. We present an application of this novel workflow to 3D defect localization in a complex 2.5D device combining high bandwidth memory (HBM) devices and an application specific integrated circuit (ASIC) unit on a Si interposer with a signal pin electrical short failure.

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

2003 ◽  
Author(s):  
Seth J. Prejean ◽  
Joseph Shannon
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Easy Access ◽  
Induced Voltage ◽  
Emission Analysis ◽  
Defect Localization ◽  
Soi Devices

Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Characterization and Simulation of a Body Biased Structure in Triple-Well Technology under Pulsed Photoelectric Laser Stimulation

2014 ◽  
Author(s):  
N. Borrel ◽  
C. Champeix ◽  
M. Lisart ◽  
A. Sarafianos ◽  
E. Kussener ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Laser Power ◽  
Pulsed Laser ◽  
Electrical Model ◽  
Activation Threshold ◽  
Laser Stimulation ◽  
Laser Illumination ◽  
High Laser ◽  
Complex Circuits

Abstract This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions inside an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed laser on a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals possible bipolar transistor activation at high laser power. This activation threshold revealed its dependence on laser power and wells biasing. Based on the measurements made during our experiments, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

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