Abstract
Time Domain Reflectrometry or TDR is an analytical technique used to determine the impedance and electrical length of conductors. This relatively inexpensive technique utilizes a pulse card and digital oscilloscope whereby the reflected signal amplitude from an initiating pulse is measured versus time. The technique is useful for characterizing the impedance of a conductor in the time domain, and has traditionally been employed in board level analysis. More recently, TDR has been shown to be useful in electrically isolating integrated circuit package failures1. Historically, open failures on non-flip chip devices were resolved through relatively straight-forward, low risk methods in a failure analysis lab. Typically, root cause analysis involved simple verification on a curve tracer, non-destructive inspection using X-Ray imaging, chemical, thermal or mechanical decapsulation, optical and electron microscopy and as necessary, the use of mechanical probe isolation. The implementation of advanced flip chip package technology rendered the traditional isolation methodologies inadequate. After verification and X-ray inspection, a decision had to be made prior to subsequent destructive physical analysis as to the most probable failure location. Since the board interconnects, board interposer, and bump locations were not geometrically aligned, isolation of opens through physical cross-sectioning became risky, tedious and lengthy. These constraints were overcome through the use of TDR analysis. The authors have successfully incorporated the TDR technique into AMD’s microprocessor failure analysis flow, improving success rate, reducing risk and decreasing turn-around time. The paper will include a brief description of TDR theory and hardware, technical barriers that the authors encountered during implementation, sample preparation as well as details where the technique was successfully employed in failure isolation. The remaining portion of this paper provides illustrative examples where TDR was effectively utilized in the analysis of slot A cards, ceramic flip chip PGA pins, and internal package trace failures.