130 nm process technology integration of advanced Cu/CVD low k dielectric material-case study of failure analysis and yield enhancement

2004 ◽  
Author(s):  
C.F. Tsang ◽  
Y.J. Su ◽  
V.N. Bliznetsov ◽  
G.T. Ang
Keyword(s):  
Technology Integration ◽  
Failure Analysis ◽  
Dielectric Material ◽  
Yield Enhancement ◽  
Process Technology ◽  
Low K

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Polishing and Cleaning of Low K Dielectric Material for ild and Damascene

2001 ◽  
Vol 671 ◽  
Author(s):  
Yuchun Wang ◽  
Rajeev Bajaj ◽  
Yongsik Moon ◽  
David Mai ◽  
Kapila Wijekoon ◽  
...  
Keyword(s):  
Dielectric Material ◽  
Removal Rate ◽  
Copper Surface ◽  
Dielectric Surface ◽  
Process Technology ◽  
Future Directions ◽  
Good Surface ◽  
Cleaning Solution ◽  
Good Surface Finish ◽  
Low K

Summary:This paper describes CMP challenges in development of copper-low k process technology. As copper/oxide or copper/FSG backend schemes are being implemented successfully in early manufacturing, development focus has shifted to Cu/OSG (organo-silicate glass) integration development. Cu-OSG presents unique challenges with CMP integration, as these films tend to have much lower hardness than silicon dioxide. Significant process challenges have to be overcome prior to successfully implementing CMP process which does not mechanically damage the softer films and at the same time can achieve planarization requirements expected from CMP process. In addition, the OSG films tend to be hydrophobic leading to a need for developing improved cleaning processes/consumables. It was determined that Applied Materials ElectraPolishTM barrier slurry is extendable to OSG films. Good removal rate and removal profile can be achieved with ElectraPolishTM slurry. A proprietary cleaning solution reduced defect counts by 2 orders of magnitude as detected by SurfScan SS6200 on blanket OSG wafers. The same cleaning solution can be applied to copper/low-k patterned damascene wafers to clean both copper and dielectric surface. Polished OSG films have RMS roughness less than 2 angstroms and copper surface roughness about 5 angstroms with good surface finish. Blanket and patterned wafer results are presented to demonstrate final capability. Future directions for process enhancement are suggested.

Dry Etch and Wet Clean Process Characterization of Ultra Low-k (ULK) Material Nanoglass®E

2004 ◽  
Vol 812 ◽  
Author(s):  
B. Ramana Murthy ◽  
C.K. Chang ◽  
Ahilakrishnamoorthy ◽  
Y.W. Chen ◽  
Ananth Naman
Keyword(s):  
Process Integration ◽  
Dielectric Material ◽  
Process Technology ◽  
Plasma Etch ◽  
K Value ◽  
Process Characterization ◽  
Voltage Ramp ◽  
Dry Etch ◽  
Low K

AbstractNANOGLASS®E (NGE) ultra low-k (ULK) dielectric material, with a k-value of ∼2.2, was integrated for 130 nm Cu/ULK interconnect process technology. This work deals with the characterization of reactive ion etching (RIE) and wet chemical processing of this film. Blanket films were characterized for etch rate, surface roughness, k-value change and chemical compatibility. Trench etching and post etch wet clean processes were developed and optimized enabling process integration for single damascene structures. Trench etch processes were evaluated for two etch schemes viz., etching under - photo resist and etching under hardmask. The details of each scheme will be described and advantages observed will be discussed. To evaluate effect of wet clean processes three different formulations were used. After formation of single damascene wafers, metal comb and serpentine structures were measured for metal continuity and bridging. Electrical continuity was achieved for long serpentine structures with 0.18μm/0.18μm line width/spacing. Based on voltage ramp test results the film was found to be sensitive to certain plasma etch conditions.

Production Yield Enhancement through Failure Analysis Investigation

2009 ◽  
Author(s):  
Rajesh Medikonduri
Keyword(s):  
Failure Analysis ◽  
Flash Memory ◽  
Production Yield ◽  
Yield Enhancement ◽  
Related Issue ◽  
Data Loss ◽  
Current Testing ◽  
Corrective Actions ◽  
The One

Abstract Production yield verification for a complex device, such as the flash memory, is a problem of primary importance due to high design density and current testing capabilities of such design. In this paper, the flow byte issue in the one time programmable block is investigated through physical failure analysis (PFA). The customer reported fail for this unit was flow byte error with flipped data loss in one of the bit. Various experiments were done on numerous units to identify the yield related issue and prevent shipment of such units to customers. The case study from this paper is beneficial to the FA community by showing the exact methodology in identifying the problem, its containment, and implementation of corrective actions on the ATE to prevent shipment of low yield units to customer. The yield was enhanced by implementing the containment and corrective actions on the ATE.

Case Study: Failure Analysis of Functional Shmoo Hole with Laser Voltage Probing

2009 ◽  
Author(s):  
S.H. Lee ◽  
Y.W. Lee ◽  
K.T. Lee ◽  
C.Y. Choi ◽  
H.W. Shin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Photon Emission ◽  
Operating Voltage ◽  
Process Technology ◽  
Time Resolved ◽  
Voltage Drops ◽  
On Chip ◽  
Metal Layers

Abstract Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes. Historically for signal probing, engineers analyzed signals from metal layers by using e-beam probing methods [1]. But due to the increased number of metal layers and the introduction of flip chip packages, new signal probing systems were developed which used time resolved photon emission (TRE) to measure signals through the backside. However, as the fabrication process technology continues to shrink, the operating voltage drops as well. When the operating voltage drops below 1.0V, signal probing systems using TRE find it harder to detect the signals [2]. Fortunately, Laser Voltage Probing (LVP) technology [3] is capable of probing beyond this limitation of TRE. In this paper, we used an LVP system to analyze and identify a functional shmoo hole failure. We also proposed the design change to prevent its reoccurrence.

Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement

2000 ◽  
Author(s):  
Cary A. Gloor
Keyword(s):  
Failure Analysis ◽  
Yield Enhancement ◽  
Standard Cell ◽  
Embedded Memory ◽  
Process Technology ◽  
Quality Performance ◽  
Root Cause ◽  
Process Characterization ◽  
System On A Chip ◽  
Made In

Abstract The advances made in process technology along with system-on-a-chip capabilities have made failure analysis ever more difficult and expensive to perform. Quick product time-to-market and the required high fabrication yields demand top quality performance from the failure analysis team. In this paper we present a methodology for embedded memory analysis (EMA) which provides design, layout, and process characterization, and yield and reliability enhancement for standard cell ASIC products. The methodology takes the power of memory testing and failure signature analysis and brings it to the logic chip to accurately predict root cause defects. We also present the application tool that is used to query, bitmap, analyze, and report the data, along with numerous case histories. This process has greatly improved failure analysis hit rates and provided much quicker turn-times for process improvement feedback and customer return root cause analysis.

Failure analysis case study on a Cu/low-k technology in package: New front-side approach using laser and plasma de-processing

2010 ◽  
Vol 50 (9-11) ◽  
pp. 1688-1691 ◽  
Author(s):  
A. Aubert ◽  
J.P. Rebrassé ◽  
L. Dantas de Morais ◽  
N. Labat ◽  
H. Frémont
Keyword(s):  
Failure Analysis ◽  
Front Side ◽  
Low K

Failure Analysis Case Study of a 1.5 Meter Space Flex Harness

2017 ◽  
Author(s):  
Erick Kim ◽  
Kamjou Mansour ◽  
Gil Garteiz ◽  
Javeck Verdugo ◽  
Ryan Ross ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Field Of View ◽  
Area Of Interest ◽  
Air Stream ◽  
Novel Method ◽  
Temperature Controlled ◽  
Non Destructive ◽  
Failure Site

Abstract This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

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