Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu IC’s

2006 ◽  
Author(s):  
Karan Kacker ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Dielectric Material ◽  
Semiconductor Industry ◽  
Cost Effective ◽  
Organic Substrate ◽  
Integrative Approach ◽  
Wafer Level ◽  
Technology Roadmap ◽  
Cte Mismatch ◽  
Compliant Interconnect ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

Challenges and approaches of ultra-fine pitch Cu pillar assembly on organic substrate using wafer level underfill

2013 ◽  
Author(s):  
Sharon Pei-Siang Lim ◽  
Li Yan Siow ◽  
Tai Chong Chai ◽  
Vempati Srinivasa Rao ◽  
Kohei Takeda ◽  
...  
Keyword(s):  
Organic Substrate ◽  
Wafer Level ◽  
Cu Pillar ◽  
Fine Pitch

Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 002082-002094
Author(s):  
Pingye Xu ◽  
Michael C. Hamilton
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Process Temperature ◽  
High Yield ◽  
Wafer Level ◽  
Micro Fabrication ◽  
Compliant Interconnect ◽  
Sac Solder

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly. Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate. In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging. The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.

Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

2010 ◽  
Vol 33 (2) ◽  
pp. 377-388 ◽  
Author(s):  
Vempati Srinivasa Rao ◽  
Xiaowu Zhang ◽  
Ho Soon Wee ◽  
Ranjan Rajoo ◽  
C S Premachandran ◽  
...  
Keyword(s):  
Wafer Level ◽  
Design And Development ◽  
Fine Pitch ◽  
Wafer Level Package ◽  
Low K

Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects

2013 ◽  
Vol 135 (3) ◽  
Author(s):  
Raphael Okereke ◽  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Cost Effective ◽  
Wafer Level ◽  
Mechanical Compliance ◽  
Interconnect Design ◽  
Compliant Interconnect ◽  
Thermomechanical Reliability ◽  
Interconnect Technology ◽  
Low K ◽  
Level Process

This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.

Alternative Compliant Interconnects: Thermo-Mechanical Reliability, Design and Testing

2001 ◽  
Author(s):  
Lunyu Ma ◽  
Qi Zhu ◽  
Suresh Sitaraman
Keyword(s):  
Low Cost ◽  
Fabrication Process ◽  
Design Parameters ◽  
Electronic Packages ◽  
Wafer Level ◽  
Free Standing ◽  
Reliability Design ◽  
Fine Pitch ◽  
Conventional Photolithography ◽  
Design And Testing

Abstract Two types of novel compliant interconnects are being proposed in this paper. The advantages of these two types of compliant interconnects are: accommodation of the mismatch due to different thermal expansions in electronic packages, integration with wafer-level fabrication process, low cost, fine pitch and high I/O density. The first type is a highly-compliant cantilevered spring interconnect for the next generation packaging and probing technology. To understand the reliability of the package with this novel compliant spring interconnect structure and the typical behavior of sliding contact, test vehicles with different orientations of the cantilevered springs (21 μm pitch) have been fabricated, assembled and subjected to thermal cycling test. In-situ resistance and temperature measurements have been conducted. The second type is a compliant free-standing interconnect, One-Turn Helix (OTH) structure. This structure is built as an one-turn strip helix in order to get good compliance in space. It can be fabricated through conventional photolithography-based IC fabrication process. Optimal design parameters have been identified for this structure taking into consideration the thermo-mechanical and electrical behavior of this unique structure.

Sign in / Sign up

Export Citation Format

Share Document