Dry Etch and Wet Clean Process Characterization of Ultra Low-k (ULK) Material Nanoglass®E

2004 ◽  
Vol 812 ◽  
Author(s):  
B. Ramana Murthy ◽  
C.K. Chang ◽  
Ahilakrishnamoorthy ◽  
Y.W. Chen ◽  
Ananth Naman
Keyword(s):  
Process Integration ◽  
Dielectric Material ◽  
Process Technology ◽  
Plasma Etch ◽  
K Value ◽  
Process Characterization ◽  
Voltage Ramp ◽  
Dry Etch ◽  
Low K

AbstractNANOGLASS®E (NGE) ultra low-k (ULK) dielectric material, with a k-value of ∼2.2, was integrated for 130 nm Cu/ULK interconnect process technology. This work deals with the characterization of reactive ion etching (RIE) and wet chemical processing of this film. Blanket films were characterized for etch rate, surface roughness, k-value change and chemical compatibility. Trench etching and post etch wet clean processes were developed and optimized enabling process integration for single damascene structures. Trench etch processes were evaluated for two etch schemes viz., etching under - photo resist and etching under hardmask. The details of each scheme will be described and advantages observed will be discussed. To evaluate effect of wet clean processes three different formulations were used. After formation of single damascene wafers, metal comb and serpentine structures were measured for metal continuity and bridging. Electrical continuity was achieved for long serpentine structures with 0.18μm/0.18μm line width/spacing. Based on voltage ramp test results the film was found to be sensitive to certain plasma etch conditions.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

Removal of Post Etch Residue on BEOL Low-K with Nanolift

2021 ◽  
Vol 314 ◽  
pp. 277-281
Author(s):  
Yuya Akanishi ◽  
Quoc Toan Le ◽  
Efrain Altamirano Sánchez
Keyword(s):  
Polymer Film ◽  
Thin Polymer Film ◽  
Particle Removal ◽  
Cleaning Process ◽  
K Value ◽  
Thin Polymer ◽  
Value Shift ◽  
Dry Etch ◽  
Removal Technique ◽  
Low K

Particle removal from BEOL low-k structures is studied using a novel particle removal technique, called Nanolift which removes particles from the substrate by forming a thin polymer film on the surface and removing the polymer film together with the particles. It was confirmed that Nanolift is capable to remove TiFx particles successfully which are generated during the low-k dry etch process for dual damascene structure formation for BEOL interconnect fabrication. Pattern collapse of the fragile low-k structure was confirmed to be prevented by Nanolift in comparison with conventional dual fluid spray cleaning method. FTIR results show that Nanolift leaves no residual polymer remain in low-k films and K-value shift by the Nanolift process was negligible and comparable with the conventional formulated chemistry cleaning process. From these results, Nanolift can be concluded as a suitable cleaning process for advanced BEOL fabrication process.

Polishing and Cleaning of Low K Dielectric Material for ild and Damascene

2001 ◽  
Vol 671 ◽  
Author(s):  
Yuchun Wang ◽  
Rajeev Bajaj ◽  
Yongsik Moon ◽  
David Mai ◽  
Kapila Wijekoon ◽  
...  
Keyword(s):  
Dielectric Material ◽  
Removal Rate ◽  
Copper Surface ◽  
Dielectric Surface ◽  
Process Technology ◽  
Future Directions ◽  
Good Surface ◽  
Cleaning Solution ◽  
Good Surface Finish ◽  
Low K

Summary:This paper describes CMP challenges in development of copper-low k process technology. As copper/oxide or copper/FSG backend schemes are being implemented successfully in early manufacturing, development focus has shifted to Cu/OSG (organo-silicate glass) integration development. Cu-OSG presents unique challenges with CMP integration, as these films tend to have much lower hardness than silicon dioxide. Significant process challenges have to be overcome prior to successfully implementing CMP process which does not mechanically damage the softer films and at the same time can achieve planarization requirements expected from CMP process. In addition, the OSG films tend to be hydrophobic leading to a need for developing improved cleaning processes/consumables. It was determined that Applied Materials ElectraPolishTM barrier slurry is extendable to OSG films. Good removal rate and removal profile can be achieved with ElectraPolishTM slurry. A proprietary cleaning solution reduced defect counts by 2 orders of magnitude as detected by SurfScan SS6200 on blanket OSG wafers. The same cleaning solution can be applied to copper/low-k patterned damascene wafers to clean both copper and dielectric surface. Polished OSG films have RMS roughness less than 2 angstroms and copper surface roughness about 5 angstroms with good surface finish. Blanket and patterned wafer results are presented to demonstrate final capability. Future directions for process enhancement are suggested.

Preparation and characterization of nanoporous polyimide membrane by the template method as low-k dielectric material

2015 ◽  
Vol 27 (3) ◽  
pp. 414-418 ◽  
Author(s):  
Sude Ma ◽  
Yan Wang ◽  
Chun Liu ◽  
Qian Xu ◽  
Zhonghua Min
Keyword(s):  
Dielectric Material ◽  
Template Method ◽  
Polyimide Membrane ◽  
Low K

Determination of Surface Energy Characteristics of Plasma Processed Ultra Low-K Dielectrics for Optimized Wetting in Wet Chemical Plasma Etch Residue Removal

2012 ◽  
Vol 195 ◽  
pp. 110-113
Author(s):  
Nicole Ahner ◽  
Sven Zimmermann ◽  
Matthias Schaller ◽  
Stefan E. Schulz
Keyword(s):  
Moisture Absorption ◽  
Plasma Processing ◽  
Reaction Products ◽  
Plasma Etch ◽  
Promising Alternative ◽  
K Value ◽  
Oh Groups ◽  
Residue Removal ◽  
Low K ◽  
Etch Residue

The integration of porous ultra low dielectric constant materials (ULK) for isolation within the interconnect system of integrated circuits is a promising approach to reduce RC-delays and crosstalk due to shrinking feature sizes [1]. Actually the focus is on porous CVD-SiCOH materials, which consist of a Si-O-Si backbone and organic species (e.g. CH3) to lower polarizability and prevent moisture uptake to remarkably decrease the k-value [2]. The integration of porous low-k materials is very challenging, especially looking at patterning, resist stripping and etch residue removal, where commonly plasma processing has been applied. But plasma processing of ULK materials, especially using oxygen plasmas, is known to degrade electrical, optical and structural material properties by removing carbon from the film and densification of the surface near areas of the ULK [5]. Carbon depletion may also lead to the incorporation of-OH groups, which easily form silanols and therefore increase moisture absorption and k-values [2]. Besides the development of nondamaging plasma processes, wet cleaning is a promising alternative to avoid ULK damage while removing organic plasma etch residues. Additionally wet cleaning steps are always necessary to remove inorganic residues, which do not form volatile reaction products and can therefore not be removed by plasma processing.

Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow

2005 ◽  
Vol 103-104 ◽  
pp. 353-356
Author(s):  
Jian She Tang ◽  
Brian J. Brown ◽  
Steven Verhaverbeke ◽  
Han Wen Chen ◽  
Jim Papanu ◽  
...  
Keyword(s):  
Process Integration ◽  
Cleaning Process ◽  
Damascene Process ◽  
Wafer Cleaning ◽  
Process Characterization ◽  
Scale Down ◽  
Metallic Contaminants ◽  
Loss Control ◽  
Wet Etch ◽  
Low K

As device features scale down to 90nm and Cu/low-k films are employed for back end interconnects, post etch and ash residue cleaning becomes increasingly challenging due to the higher aspect ratio of the features, tighter CD control requirements, sensitivity of the low-k films, and the requirement for high wet etch selectivity between CuxO and Cu. Traditional solvent based cleaning in wet benches has additional issues such as wafer cross-contamination and high disposal cost [1, 2]. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these challenges. The results of physical characterization, process integration electrical data, and process integration reliability data such as electromigration (EM) and stress migration data are presented. The main conclusions can be summarized as follows: (1) The single wafer cleaning process developed on the Oasis™ system can clean post etch residues and simultaneously clean the wafer front side and backside metallic contaminants; (2) In terms CuxO and Cu wet etch selectivity, CD loss control, the Oasis™ aqueous single wafer clean process is superior to the bench solvent cleaning process; (3)The Oasis aqueous cleaning process shows no undercut below etchstop due to the very low Cu etch amount in one cleaning pass, therefore the electromigration and stress migration performance of the aqueous Oasis processed wafers is clearly better than that of the solvent bench processed wafers.

scholarly journals Magnetoresistance Recovery in the Amorphous Dielectric Material SiCOH

2021 ◽  
pp. 9-17
Author(s):  
Philip A. Williams ◽  
James R. Lloyd
Keyword(s):  
Electric Field ◽  
Dielectric Material ◽  
Charge Carriers ◽  
Charge Accumulation ◽  
Trap States ◽  
Spin Singlet ◽  
Amorphous Dielectric ◽  
Electrical Bias ◽  
Low K

The use of a magnetoresistance in the characterization of transport properties in the amorphous low-k dielectric material SiCOH is demonstrated. The double occupancy of charge carriers in trap states within the dielectric material can only exist in spin singlet formation due to Pauli Exclusion. The trap-assisted negative magnetoresistance (MR) in amorphous SiCOH, driven by an applied electric field that results in an observed increase in magnitude of the current in the conduction band is due to singly occupied trap spin-mixing suppression of carriers with the application of an external magnetic field. The material MR decays with time under electrical bias and temperature stress as traps are filled by charge carriers and from space charge accumulation. The MR can be reinstated by the ionization of these traps via the conduction mechanisms of nonthermally activated tunneling and thermal ionization with the assistance of an applied coulombic potential barrier lowering electric field. In this work a direct correlation is shown between a material MR and the trapping, de-trapping, and trap avoidance of singly occupied traps in the transport of charge carriers in the amorphous low-k dielectric material SiCOH (a-SiCOH).

Sign in / Sign up

Export Citation Format

Share Document