Case Study: Failure Analysis of Functional Shmoo Hole with Laser Voltage Probing

2009 ◽  
Author(s):  
S.H. Lee ◽  
Y.W. Lee ◽  
K.T. Lee ◽  
C.Y. Choi ◽  
H.W. Shin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Photon Emission ◽  
Operating Voltage ◽  
Process Technology ◽  
Time Resolved ◽  
Voltage Drops ◽  
On Chip ◽  
Metal Layers

Abstract Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes. Historically for signal probing, engineers analyzed signals from metal layers by using e-beam probing methods [1]. But due to the increased number of metal layers and the introduction of flip chip packages, new signal probing systems were developed which used time resolved photon emission (TRE) to measure signals through the backside. However, as the fabrication process technology continues to shrink, the operating voltage drops as well. When the operating voltage drops below 1.0V, signal probing systems using TRE find it harder to detect the signals [2]. Fortunately, Laser Voltage Probing (LVP) technology [3] is capable of probing beyond this limitation of TRE. In this paper, we used an LVP system to analyze and identify a functional shmoo hole failure. We also proposed the design change to prevent its reoccurrence.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Failure Analysis of Advanced Microprocessors through Backside Approaches

1998 ◽  
Author(s):  
D. Davis ◽  
O. Diaz de Leon ◽  
L. Hughes ◽  
S. V. Pabbisetty ◽  
R. Parker ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Preparation Methods ◽  
Analysis Techniques ◽  
Analytical Approaches ◽  
Sample Preparation Methods ◽  
New Devices

Abstract The advent of Flip Chip and other complex package configurations and process technologies have made conventional failure analysis techniques inapplicable. This paper covers the ways in which conventional techniques have been modified to meet the FA challenges presented by these new devices – specifically, by forcing analysis to be done from the backside of the device. Modifications to the traditional FA process steps, including new sample preparation methods, changes in hardware, and alterations to physical failure analysis processes are described. To demonstrate the use of backside analytical approaches, some examples of applications and a case study are also included.

Backside EBIRCH Defect Localization for Advanced Flip-Chip Failure Analysis

2021 ◽  
Author(s):  
Chuan Zhang ◽  
Jane Y. Li ◽  
John Aguada ◽  
Howard Marks
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Flip Chips ◽  
Defect Localization ◽  
Localization Approach

Abstract This paper introduced a novel defect localization approach by performing EBIRCH isolation from backside of flip-chips. Sample preparation and probing consideration was discussed, and then a case study was used to illustrate how the backside EBIRCH technique provides a powerful solution in capturing and root-causing subtle defects in challenging flip-chip failures.

Defect Localization Using Time-Resolved Photon Emission on SOI Devices that Fail Scan Tests

2002 ◽  
Author(s):  
Dan Bodoh ◽  
Ed Black ◽  
Kris Dickson ◽  
Ron Wang ◽  
Tim Cheng ◽  
...  
Keyword(s):  
Case Studies ◽  
Flip Chip ◽  
Near Infrared ◽  
Photon Emission ◽  
Silicon On Insulator ◽  
Time Resolved ◽  
Defect Localization ◽  
Emission System ◽  
Soi Devices ◽  
Practice Time

Abstract Time-resolved photon emission has been shown to be useful in analyzing clock skews and timing-related defects in flip-chip devices. In practice, time-resolved photon emission using the S-25 Quantar detector cannot be used at long loop lengths (typically >10 μs). This paper discusses a near-infrared (NIR) optimized time-resolved emission system to demonstrate that even with long loop lengths time-resolved photon emission can be extremely useful for defect localization. Specifically, it describes time-resolved photon emission system, and shows how time-resolved photon emission was used to solve two different issues that caused scan fails on silicon-on-insulator devices, and briefly discusses the interpretation of optical waveforms. The two issues are presented as case studies.

Failure Analysis from the Backside of a Die

2000 ◽  
Author(s):  
Silke Liebert
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Gate Oxide ◽  
Physical Analysis ◽  
Back Side ◽  
Bulk Silicon ◽  
Analysis Methods ◽  
On Chip ◽  
Voltage Contrast ◽  
Side Flow

Abstract A back side failure analysis flow has been developed in order to enable failure analysis of flip-chip, lead-on-chip dies and within multi-metal-level dies. A combination with frontside failure analysis methods is possible too. The back side flow consists of stepwise bulk silicon removal, electrical and physical failure analysis methods. Four different methods for bulk silicon thinning in order to localize electrical defects using PEM are compared. A method to remove the bulk silicon after PEM analysis to expose the gate oxide level of a die has been developed. Different back side applications like physical analysis of gate oxide defects, passive voltage contrast and microprobing with an AFM tip for detection of interrupts within conductive interconnects are described.

Application of the Infrared Microscope (IREM1) for Flip-Chip (C4) Failure Analysis

1999 ◽  
Author(s):  
A. N. Zaplatin ◽  
F. J. Low ◽  
Steve Seidel ◽  
Valluri R. Rao ◽  
T. H. Loh
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Flip Chip ◽  
Hot Spot ◽  
Spectral Response ◽  
Real Life ◽  
Fault Isolation ◽  
Front Side ◽  
Process Technology ◽  
Ir Emission

Abstract Today’s process technology requires ever-increasing number of metal layers to meet the power and layout needs of modern products. These advances have rendered many of the conventional fault isolation (FI) methods from the front side of the die obsolete. The flip-chip package not only brings about the need to localize defects at die level through the Si substrate, but also introduces the need to isolate new defects at the package level. Recently, an infrared (IR) emission microscope which utilizes the cryogenically cooled HgCdTe (MCT) imaging array having spectral response of 0.8μm- 2.5μm, for near IR emission detection was developed. This system supersedes the conventional CCD based emission microscope with a spectral response of 0.4 μm-1.1μm. Since spectral detection extends into the thermal spectral region, it also offers an added advantage of detecting thermal spots on the die and flip-chip package where liquid crystal hot spot detection method is not possible. This article is an account of the use of the Mercury-Cadmium- Telluride based IR detector for “real life” failures. The article will demonstrate key features of the system as well as several FI examples. Both emission and thermal detection modes will be discussed. The authors will present several problems, including melted die bumps and package copper trace shorts, that could not be detected through conventional failure analysis (FA) methods, such as liquid crystal or front side emission microscopy. The MCT detectors increased sensitivity and backside navigation capabilities coupled with backside die preparation has proven itself an indispensable FA tool in the high volume manufacturing environment.

scholarly journals A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

2012 ◽  
Vol 2012 ◽  
pp. 1-9 ◽  
Author(s):  
Jacob Postman ◽  
Patrick Chiang
Keyword(s):  
System Integration ◽  
Energy Efficient ◽  
State Of The Art ◽  
Error Correcting Codes ◽  
Cmos Process ◽  
Process Technology ◽  
Interconnect Reliability ◽  
On Chip ◽  
Communication Demands

Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication demands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a review of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.

Failure Analysis Case Study of Inductively Coupled Cross-Chip Signals

2016 ◽  
Author(s):  
Steven Loveless ◽  
Zhihong You ◽  
Tathagata Chatterjee ◽  
Badarish Subbannavar
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Individual Data ◽  
Cause Analysis ◽  
Inductively Coupled ◽  
Root Cause ◽  
Specific Device ◽  
Data Points ◽  
On Chip

Abstract This paper discusses a failure analysis case study in a highly integrated mixed signal device caused by inductive coupling of on-chip signals. The techniques utilized and the approach to root cause analysis are discussed in depth. The interactions between the device design and failure mechanism are identified in detail. Focus is placed on drawing conclusions from the sum of individual data points, and the discussion provides an analytical path by which similar failures can be isolated and specific device sensitivities can be identified.

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