Polishing and Cleaning of Low K Dielectric Material for ild and Damascene

2001 ◽  
Vol 671 ◽  
Author(s):  
Yuchun Wang ◽  
Rajeev Bajaj ◽  
Yongsik Moon ◽  
David Mai ◽  
Kapila Wijekoon ◽  
...  
Keyword(s):  
Dielectric Material ◽  
Removal Rate ◽  
Copper Surface ◽  
Dielectric Surface ◽  
Process Technology ◽  
Future Directions ◽  
Good Surface ◽  
Cleaning Solution ◽  
Good Surface Finish ◽  
Low K

Summary:This paper describes CMP challenges in development of copper-low k process technology. As copper/oxide or copper/FSG backend schemes are being implemented successfully in early manufacturing, development focus has shifted to Cu/OSG (organo-silicate glass) integration development. Cu-OSG presents unique challenges with CMP integration, as these films tend to have much lower hardness than silicon dioxide. Significant process challenges have to be overcome prior to successfully implementing CMP process which does not mechanically damage the softer films and at the same time can achieve planarization requirements expected from CMP process. In addition, the OSG films tend to be hydrophobic leading to a need for developing improved cleaning processes/consumables. It was determined that Applied Materials ElectraPolishTM barrier slurry is extendable to OSG films. Good removal rate and removal profile can be achieved with ElectraPolishTM slurry. A proprietary cleaning solution reduced defect counts by 2 orders of magnitude as detected by SurfScan SS6200 on blanket OSG wafers. The same cleaning solution can be applied to copper/low-k patterned damascene wafers to clean both copper and dielectric surface. Polished OSG films have RMS roughness less than 2 angstroms and copper surface roughness about 5 angstroms with good surface finish. Blanket and patterned wafer results are presented to demonstrate final capability. Future directions for process enhancement are suggested.

Surfactants in Controlling Removal Rates and Selectivity in Barrier Slurry for Cu CMP

2007 ◽  
Vol 991 ◽  
Author(s):  
Jinru Bian
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Removal Rate ◽  
Leading Edge ◽  
Dielectric Surface ◽  
Wafer Surface ◽  
Capping Layer ◽  
Charge Interaction ◽  
High Removal Rate ◽  
Low K

ABSTRACTLeading edge integrated circuits (ICs) are complicated structures designed to have up to 3 capping layers above a low k dielectric material. The upper capping layer may use TEOS and/or silicon nitride (SiN), while the lower one may use silicon carbon nitride (SiCN), silicon carbide (SiC), or carbon doped oxide (CDO) immediately above the low k dielectric. Therefore, a barrier slurry for copper CMP, in addition to exhibiting a high removal rate of the barrier, must be able to remove the upper capping layer and stop at the underlying dielectric surface.We have developed a slurry family that can effectively remove TaN, TEOS, SiN, CDO, and/or SiCN, or any combination of these films, or can stop at any one or two film surfaces of TEOS, SiN, CDO, SiCN, and SiC, depending on the specific slurry design. Removal rate control is achieved by one or two additives. One of the additives is an anionic surfactant. When selecting a surfactant, the surfactant hydrophobicity and charge interaction between the surfactant and the wafer surface are two important factors to be considered. This report discusses these two factors in selecting a proper surfactant for a specific slurry application.

Performance and Analysis of Silicon Mixed Kerosene Servotherm in EDM of Monel 400

2015 ◽  
Vol 766-767 ◽  
pp. 674-680
Author(s):  
P. Karunakaran ◽  
J. Arun ◽  
V. Palanisamy ◽  
N.R.R. Anbusagar ◽  
P. Sengottuvel
Keyword(s):  
Surface Finish ◽  
Material Removal ◽  
Removal Rate ◽  
Silicon Powder ◽  
Graphite Powder ◽  
Dielectric Medium ◽  
Tool Wear Rate ◽  
Good Surface ◽  
Good Surface Finish ◽  
Monel 400

Improving the Material Removal Rate (MRR), reduce Tool Wear Rate (TWR), achieve the good Surface Finish (SF) and Over Cut (OC) are very demanding in Electrical Discharging Machining (EDM). This paper focused on performance of Silicon powder mixed with kerosene servotherm dielectric medium in EDM of Monel 400. The optimum range of Silicon powder, Graphite powder 6g mixes with the dielectric medium of kerosene servotherm (75:25) were developed experimentally. It was reported slightly more MRR, very low TWR, better OC and good surface finish (SF) in Monel 400.

Development of Advanced Broaching Tool for Machining Titanium Alloy

2012 ◽  
Vol 445 ◽  
pp. 161-166
Author(s):  
Mohammed Sarwar ◽  
Mike Dinsdale ◽  
Julfikar Haider
Keyword(s):  
Surface Quality ◽  
Metal Removal ◽  
Removal Rate ◽  
Cutting Tools ◽  
Vital Role ◽  
Tool Geometry ◽  
Depth Of Cut ◽  
Good Surface ◽  
Tool Performance ◽  
Good Surface Finish

Broaching is a precision multipoint metal removal operation normally employed for manufacturing variety of complex parts having either internal or external features. Broaching can produce high precision and good surface finish at a high metal removal rate. The unique feature of a broach tool is that the feed/depth of cut for the teeth is built into the broach unlike other cutting tools. The tool design (e.g., rise per tooth and tooth geometry) play a vital role in the broach performance. A specially adapted machine tool modified to investigate a single broach tooth has been used. Cutting forces and material removal rate have been measured during experimental work for different combination of broaching parameters and broach tool geometry. The effect of the parameters on the surface quality produced has been established. The characteristics of chips formed have also been defined. Finally, optimum tooth geometry and rise per tooth have been recommended for tool performance, broached surface quality and efficient chip formation. The information provided in this paper will be beneficial for broach tool designers and manufacturing engineers.

Dry Etch and Wet Clean Process Characterization of Ultra Low-k (ULK) Material Nanoglass®E

2004 ◽  
Vol 812 ◽  
Author(s):  
B. Ramana Murthy ◽  
C.K. Chang ◽  
Ahilakrishnamoorthy ◽  
Y.W. Chen ◽  
Ananth Naman
Keyword(s):  
Process Integration ◽  
Dielectric Material ◽  
Process Technology ◽  
Plasma Etch ◽  
K Value ◽  
Process Characterization ◽  
Voltage Ramp ◽  
Dry Etch ◽  
Low K

AbstractNANOGLASS®E (NGE) ultra low-k (ULK) dielectric material, with a k-value of ∼2.2, was integrated for 130 nm Cu/ULK interconnect process technology. This work deals with the characterization of reactive ion etching (RIE) and wet chemical processing of this film. Blanket films were characterized for etch rate, surface roughness, k-value change and chemical compatibility. Trench etching and post etch wet clean processes were developed and optimized enabling process integration for single damascene structures. Trench etch processes were evaluated for two etch schemes viz., etching under - photo resist and etching under hardmask. The details of each scheme will be described and advantages observed will be discussed. To evaluate effect of wet clean processes three different formulations were used. After formation of single damascene wafers, metal comb and serpentine structures were measured for metal continuity and bridging. Electrical continuity was achieved for long serpentine structures with 0.18μm/0.18μm line width/spacing. Based on voltage ramp test results the film was found to be sensitive to certain plasma etch conditions.

Experimental Investigation of Machining Parameters on Surface Roughness in Dry and Wet Wire-Electrical Discharge Machining

2011 ◽  
Vol 264-265 ◽  
pp. 831-836 ◽  
Author(s):  
Suleiman Abdulkareem ◽  
Ahsan Ali Khan ◽  
Zakaria Mohd Zain
Keyword(s):  
Surface Roughness ◽  
Electrical Discharge ◽  
Electrical Discharge Machining ◽  
Removal Rate ◽  
Local Heating ◽  
Wire Electrical Discharge Machining ◽  
Machining Parameters ◽  
Good Surface ◽  
Good Surface Finish ◽  
Wedm Process

Wire electrical discharge machining (WEDM) is a thermal process in which the workpiece and the wire (tool) experience an intense local heating in the discharge channel. The high power density results in the erosion of a part of the material from both electrodes by local melting and vaporization. Whilst good surface finish and high material removal rate of the workpiece is a major requirement, the effect of EDM machining factors on these requirements cannot be overlooked. This study investigate the effect of two different machining methods of dry and wet WEDM process as well as the effect of on-time and voltage on the surface roughness of the workpiece. The machining factors used for this study are the pulse current, on-time and voltage. The results of the effect of the two machining methods on the responses are investigated and reported in this paper.

Experimental Investigation on Chemical-Mechanical Polishing of Wafers With Low-Conductivity Dielectrics

2001 ◽  
Author(s):  
Jhy-Cherng Tsai ◽  
Charls Liu ◽  
Ming-Hsih Tsai ◽  
Bao-Tong Dai
Keyword(s):  
Chemical Mechanical Polishing ◽  
Material Removal ◽  
Sandwich Structure ◽  
Dielectric Material ◽  
Removal Rate ◽  
Mechanical Polishing ◽  
Wafer Surface ◽  
Key Technologies ◽  
Semiconductor Fabrication ◽  
Low K

Abstract Low conductivity (low-k) dielectric material is used in the sandwich structure of next-generation semiconductor devices in order to reduce the RC time delay. While global flatness of wafer surface becomes critical for deep sub-micro semiconductor fabrication process, chemical-mechanical polishing (CMP) becomes one of the key technologies for planarization of wafer surface. This paper investigated the effect of the low-k material on the CMP of the SiO2 cap layer of such a sandwiched wafer. Two types of wafers, blanket wafer and wafer with circuit pattern, are designed and conducted to investigate the effects of the thickness of the low-k layer under different polishing pressures and velocities. Material removal rate (RR) and non-uniformity (NU) are used as indices of the CMP process performance. The results show that the RR and NU of wafers with low-k layer, either blanket or with circuit pattern, become better when the pressure or velocity increases. The thickness of the low-k layer, however, has only tiny effect on the RR and NU.

Low-K Dielectric Material Chemical Mechanical Polishing Process Monitoring using Acoustic Emission

1997 ◽  
Vol 476 ◽  
Author(s):  
Jianshe Tang ◽  
Carsten Unger ◽  
Yongsik Moon ◽  
David Dornfeld
Keyword(s):  
Surface Roughness ◽  
Acoustic Emission ◽  
Material Removal Rate ◽  
Material Removal ◽  
Dielectric Material ◽  
Removal Rate ◽  
Wafer Surface ◽  
Low K ◽  
Ae Signals

AbstractLow-k dielectric material removal rate, which is significantly affected by process factors such as polishing load, wafer carrier rotation, platen rotation speed and pad age, is one of the critical issues in CMP planarization of a dielectric film when concerning productivity, throughputs and stabilization of the process, especially when trying to achieve a target polishing thickness. Scratching is another critical issue in low-k dielectric filmi CMP planarization due to the lower hardness relative to silicon dioxide. This research relates to a methodology for in-situ monitoring of the low-k dielectric material CMP planarization process, specifically for monitoring material removal rate and scratch occurrence, using acoustic emission (AE) sensing technology.Systematic investigations of CMP process variables on AE signals were carried out in this research. The sensitivity of AE to polishing load, polishing speed, wafer surface roughness (wafer pattern density) and pad roughness were verified. The results showed that, under steady state, the AE rms signal increases with increasing polishing load, polishing speed, slurry particle size, wafer surface roughness and pad roughness.Based on the research in tribology and other application fields of loose abrasive machining such as lapping and polishing, scratching was known to be caused by the presence of particles which are much larger than average slurry particles. It has been proven that scratching can be avoided or reduced by timely cleaning the slurry supply system. Therefore, to avoid scratching, one strategy is to develop an in-situ method for detecting larger particles involved in CMP process. In this paper, the high sensitivity of AE signals to the presence of larger particles during CMP was experimentally verified.

CONTINUOUS-CAST 45-12 DUCTILE IRON

Alloy Digest ◽  
1989 ◽  
Vol 38 (4) ◽  
Keyword(s):  
Continuous Casting ◽  
Ductile Iron ◽  
Heat Treating ◽  
Grain Structure ◽  
Continuous Cast ◽  
Good Surface ◽  
Fine Grain ◽  
High Speeds ◽  
Good Surface Finish ◽  
Iron Grade

Abstract Ductile Iron grade 45-12 produced by continuous casting has consistent density and fine grain structure. It is the softest of the regular grades of ductile iron and it machines at high speeds with good surface finish. This datasheet provides information on composition, physical properties, microstructure, hardness, elasticity, and tensile properties. It also includes information on heat treating, machining, and joining. Filing Code: CI-58. Producer or source: Federal Bronze Products Inc..

The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

1999 ◽  
Vol 565 ◽  
Author(s):  
N. Ariel ◽  
M. Eizenberg ◽  
E. Y. Tzou
Keyword(s):  
Amorphous Carbon ◽  
Nuclear Reactions ◽  
Dielectric Material ◽  
Copper Metallization ◽  
Limiting Factor ◽  
Adhesion Promoter ◽  
Adhesion Promotion ◽  
High Resolution Tem ◽  
Rc Delay ◽  
Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the Cls transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

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