MOSFET implant failure analysis using plane-view scanning capacitance microscopy coupled with nano-probing and TCAD modeling

2014 ◽  
Author(s):  
Hun-Seong Choi ◽  
Yong-Woon Han ◽  
Il-Sub Chung
Keyword(s):  
Failure Analysis ◽  
Implant Failure ◽  
Scanning Capacitance Microscopy ◽  
Plane View

Scanning Capacitance Microscopy Application for Bipolar and CMOS Doping Issues in Semiconductor Failure Analysis

2005 ◽  
Author(s):  
Coswin Lin ◽  
Homy Ou ◽  
Chia-Hsing Chao ◽  
Shey-Shi Lu
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Cross Section ◽  
Layer By Layer ◽  
Localization Method ◽  
Scanning Capacitance Microscopy ◽  
Leakage Path ◽  
Schematic Cross Section ◽  
Power Leakage ◽  
Plane View

Abstract Scanning Capacitance Microscopy (SCM) has been extensively used for identifying doping issues in semiconductor failure analysis. In this paper, the root causes of two recent problems -- bipolar beta loss and CMOS power leakage -- were verified using SCM images. Another localization method, layer-by-layer circuit repair with IROBIRCH detection, was also utilized to locate possible defects. The resulting failure mechanism for bipolar beta loss is illustrated with a schematic cross section, which shows the leakage path from the emitter to the base. In the case of CMOS power leakage, the abnormal implantation of the Pwell region was identified with the Plane view SCM image.

Front-End Failure Analysis of Integrated Circuits Using Scanning Capacitance Microscopy

2004 ◽  
Author(s):  
M.C. Huang ◽  
C.T. Lin ◽  
J.C. Lin
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Channel Length ◽  
Cross Sectional ◽  
Scanning Capacitance Microscopy ◽  
Front End ◽  
Low Threshold ◽  
Power Leakage ◽  
Plane View ◽  
Better Than

Abstract Scanning capacitance microscopy (SCM), a powerful technique to identify front-end defects, is also helpful in understanding failure mechanisms. This article discusses three front-end doping failure examples that were clearly identified by SCM analysis. The first example was NMOS leakage between drain and source. SCM images showed that N+ junction distortion resulted in effective channel length shortage. The second one was by-field SRAM failure with power leakage. From SCM images, it is clarified that P-well was directly short to P+ in bad die and slight P-well boundary shift to P+ was observed in good die. The third example was regarding low threshold voltage failure analysis. It illustrates that combination of plane-view and cross-sectional SCM analysis could help to diagnose the failure mechanism. The resolution and precision in SCM is better than that in chemical etching combined with SEM technique.

Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

2018 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Tanya Schaeffer ◽  
Yuting Wei ◽  
Satish Kodali ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Scanning Capacitance Microscopy ◽  
Force Microscopy ◽  
Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

To Reveal Invisible Doping Defect by Nanoprobing Analysis, Scanning Capacitance Microscopy, and Simulation

2017 ◽  
Author(s):  
LiLung Lai ◽  
Li Yang ◽  
Chunhui Wang ◽  
Yong Wu
Keyword(s):  
Failure Analysis ◽  
Material Composition ◽  
Doping Profile ◽  
New Techniques ◽  
Great Opportunity ◽  
Scanning Capacitance Microscopy ◽  
Electrical Modeling ◽  
Scale Dimension ◽  
Physical Defects ◽  
Trace Concentrations

Abstract Modern techniques of semiconductor physical failure analysis are effective at revealing physical defects and device material composition, however, dopant profiles/ concentrations are not easily determined since these materials are in trace concentrations. Therefore, defects related to dopants are often referred to as invisible defects. New techniques have been incorporated into failure analysis to reveal the invisible defects resulting from electrical carriers (via SCM/SSRM) and physical doping profile (via STEM/EDS) in nm-scale dimension. Using nanoprobing analysis, simulation for electrical modeling, along with EDS and SCM for physical profiling, we have a great opportunity to uncover abnormal doping issues allowing completion of the failure analysis and the execution of corrective actions.

Guidelines for Two-Dimensional Dopant Profiling Using Scanning Capacitance Microscopy

2000 ◽  
Author(s):  
Axel Born ◽  
R. Wiesendanger
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Edge Effects ◽  
Two Dimensional ◽  
Stray Capacitance ◽  
Scanning Capacitance Microscopy ◽  
Dopant Profiling ◽  
3D Geometry ◽  
Cv Measurements ◽  
Preparation Techniques

Abstract This paper provides guidance and insights on the use of scanning capacitance microscopy (SCM) in semiconductor failure analysis. It explains why SCM systems are constrained by rigid performance tradeoffs and how CV measurements are affected by large stray capacitance and as well as edge effects associated with the 3D geometry of the sample and probe. It also explains how samples should be prepared and how proper sample preparation techniques combined with optimally selected voltages make it possible to accurately determine doping concentrations, even in p-n junctions.

Scanning Capacitance Microscopy Use in the Failure Analysis of Vcc Shorts in an Advanced Microprocessor

1998 ◽  
Author(s):  
Kendall Scott Wills ◽  
Hal Edwards ◽  
Long Nuygen ◽  
Rohini Raghunathan ◽  
Charles Todd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Frequency ◽  
Dry Etching ◽  
Gate Length ◽  
Ozone Oxidation ◽  
Unique Pattern ◽  
Scanning Capacitance Microscopy ◽  
Poly Silicon ◽  
The Cost ◽  
Uv Ozone

Abstract This article analyzes the cause of Vcc shorts in advanced microprocessors. In one instance, an advanced microprocessor exhibited Vcc shorts at wafer sort in a unique pattern. The poly silicon was narrow in one section of the die. The gates were shown to measure small, but no electrical proof of the short could be seen. To prove the short existed as a result of the narrow gate, a Scanning Capacitance Microscope (SCM) was utilized to confirm electrical models, which indicated a narrow poly silicon gate would result in Vcc shorts. High frequency dry etching and UV-ozone oxidation were employed for deprocessing. The use of the SCM confirmed the proof that the Vcc shorts were caused by narrow gate length which causes its leaky behavior. This conclusion could have only been confirmed by processing of material through the wafer foundry at the cost of money and time.

Scanning Capacitance Microscopy for Failure Analysis of SOI-Based Advanced Microprocessors

2010 ◽  
Author(s):  
Lim Soon Huat ◽  
Lwin Hnin-Ei ◽  
Vinod Narang ◽  
J.M. Chin
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
Large Area ◽  
Scanning Capacitance Microscopy ◽  
Electrical Failure ◽  
Silicon Transistors ◽  
Soi Substrates ◽  
Electrical Data

Abstract Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

scholarly journals Advanced Physical Failure Analysis Techniques Using 3D Rotation Imaging from Plane-View TEM Sample

2011 ◽  
Vol 17 (S2) ◽  
pp. 634-635
Author(s):  
H-J Kang ◽  
J-G Gwak ◽  
T-S Park ◽  
T-S Back ◽  
H-J Kim ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Analysis Techniques ◽  
Plane View

Extended abstract of a paper presented at Microscopy and Microanalysis 2011 in Nashville, Tennessee, USA, August 7–August 11, 2011.

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