Front-End Failure Analysis of Integrated Circuits Using Scanning Capacitance Microscopy

2004 ◽  
Author(s):  
M.C. Huang ◽  
C.T. Lin ◽  
J.C. Lin
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Channel Length ◽  
Cross Sectional ◽  
Scanning Capacitance Microscopy ◽  
Front End ◽  
Low Threshold ◽  
Power Leakage ◽  
Plane View ◽  
Better Than

Abstract Scanning capacitance microscopy (SCM), a powerful technique to identify front-end defects, is also helpful in understanding failure mechanisms. This article discusses three front-end doping failure examples that were clearly identified by SCM analysis. The first example was NMOS leakage between drain and source. SCM images showed that N+ junction distortion resulted in effective channel length shortage. The second one was by-field SRAM failure with power leakage. From SCM images, it is clarified that P-well was directly short to P+ in bad die and slight P-well boundary shift to P+ was observed in good die. The third example was regarding low threshold voltage failure analysis. It illustrates that combination of plane-view and cross-sectional SCM analysis could help to diagnose the failure mechanism. The resolution and precision in SCM is better than that in chemical etching combined with SEM technique.

Scanning Capacitance Microscopy Application for Bipolar and CMOS Doping Issues in Semiconductor Failure Analysis

2005 ◽  
Author(s):  
Coswin Lin ◽  
Homy Ou ◽  
Chia-Hsing Chao ◽  
Shey-Shi Lu
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Cross Section ◽  
Layer By Layer ◽  
Localization Method ◽  
Scanning Capacitance Microscopy ◽  
Leakage Path ◽  
Schematic Cross Section ◽  
Power Leakage ◽  
Plane View

Abstract Scanning Capacitance Microscopy (SCM) has been extensively used for identifying doping issues in semiconductor failure analysis. In this paper, the root causes of two recent problems -- bipolar beta loss and CMOS power leakage -- were verified using SCM images. Another localization method, layer-by-layer circuit repair with IROBIRCH detection, was also utilized to locate possible defects. The resulting failure mechanism for bipolar beta loss is illustrated with a schematic cross section, which shows the leakage path from the emitter to the base. In the case of CMOS power leakage, the abnormal implantation of the Pwell region was identified with the Plane view SCM image.

Fabrication of Planar and Cross-Sectional TEM Specimens Using a Focused Ion Beam

1990 ◽  
Vol 199 ◽  
Author(s):  
R. J. Young ◽  
E. C. G. Kirk ◽  
D. A. Williams ◽  
H. Ahmed
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Cross Sectional ◽  
Transmission Electron ◽  
A New Technique ◽  
Sectional Analysis ◽  
Selection Of ◽  
Better Than

ABSTRACTA new technique using a focused ion beam has been developed for the fabrication of transmission electron microscopy specimens in pre-selected regions. The method has been proven in the fabrication of both cross-sectional and planar specimens, with no induced artefacts. The lateral accuracy achievable in the selection of an area for cross-sectional analysis is better than one micrometre. The technique has been applied to a number of silicon and III-V based integrated circuits, and is expected to be suitable for many other materials and structures.

A Selected Area Planar TEM (SAPTEM) Sample Preparation Procedure for Failure Analysis of Integrated Circuits

1998 ◽  
Author(s):  
S. Subramanian ◽  
P. Schani ◽  
E. Widener ◽  
P. Liston ◽  
J. Moss ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Ion Beam ◽  
Preparation Technique ◽  
Mechanical Grinding ◽  
Cross Sectional ◽  
Plan View ◽  
The Cross

Abstract A selected area planar TEM (SAPTEM) sample preparation technique for failure analysis of integrated circuits using a transmission electron microscope has been developed. The technique employs a combination of mechanical grinding, selective wet/dry chemical etching (if required) and a two step focused ion beam IIFIB) milling. The mechanical grinding steps include: (a) a backside grind to achieve a die thickness less than 30 µm, (b) the support half ring glue, and (c) a cross-section grind from one side to reach less than 35 pm to the failing site. A selective wet or dry chemical etch is applied before, between,, or after FIB thinning depending on the nature of problem and device components. The FIB milling steps involve: (is) a high ion current cross-sectional cut to reach as close as 5-8 µm to the area of interest (b) a final planar thinning with the ion beam parallel to the surface of the die. The plan view procedure offers unique geometric advantage over the cross-section method for failure analysis of problems that are limited to silicon or certain layers of the device. Iln the cross-sectional approach, a thin section (thickness less than 250 µm) of a device is available for failure analysis, whereas in the planar procedure a 20 µm2 area of any layer (thickness less than 250 µm) of the device is available. The above advantage has been successfully exploited to identify and solve the following prablems in fast static random access memories (FSRAM): (i) random gateoxide rupture that resulted in single bit failures, (ii) random dislocations from the buried contact trenching that caused single bit failures and general silicon defectivity (e.g. implant damage and spacer edge defects), and (iii) interracial reactions.

Failure Analysis With the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 482-483
Author(s):  
John R. Devaney
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
High Reliability ◽  
Military Applications ◽  
Small Structure ◽  
Useful Life ◽  
Insight Into ◽  
Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

Characterization of Rh/Si multilayer structure by HREM and HAADF

1992 ◽  
Vol 50 (1) ◽  
pp. 122-123
Author(s):  
Y. Cheng ◽  
J. Liu ◽  
M.B. Stearns ◽  
D.G. Steams
Keyword(s):  
Normal Incidence ◽  
High Resolution Electron Microscopy ◽  
X Rays ◽  
Beam Direction ◽  
Cross Sectional ◽  
Optical Elements ◽  
Resolution Electron ◽  
Point To Point ◽  
Better Than

The Rh/Si multilayer (ML) thin films are promising optical elements for soft x-rays since they have a calculated normal incidence reflectivity of ∼60% at a x-ray wavelength of ∼13 nm. However, a reflectivity of only 28% has been attained to date for ML fabricated by dc magnetron sputtering. In order to determine the cause of this degraded reflectivity the microstructure of this ML was examined on cross-sectional specimens with two high-resolution electron microscopy (HREM and HAADF) techniques.Cross-sectional specimens were made from an as-prepared ML sample and from the same ML annealed at 298 °C for 1 and 100 hours. The specimens were imaged using a JEM-4000EX TEM operating at 400 kV with a point-to-point resolution of better than 0.17 nm. The specimens were viewed along Si [110] projection of the substrate, with the (001) Si surface plane parallel to the beam direction.

Circuit Voltage Probe Based on Time-Integrated Measurements of Optical Emission From Leakage Current

2002 ◽  
Author(s):  
Franco Stellari ◽  
Peilin Song ◽  
James C. Tsang ◽  
Moyra K. McManus ◽  
Mark B. Ketchen
Keyword(s):  
Leakage Current ◽  
Voltage Drop ◽  
Optical Emission ◽  
Channel Length ◽  
Operating Conditions ◽  
Power Circuit ◽  
Hot Carrier ◽  
Optical Inspection ◽  
Low Threshold ◽  
Circuit Power

Abstract Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

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