A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology

2017 ◽  
Author(s):  
Somnath Kundu ◽  
Chris H. Kim
Keyword(s):  
Cmos Technology ◽  
Multi Phase

scholarly journals Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

2003 ◽  
Vol 1 ◽  
pp. 243-246 ◽  
Author(s):  
A. Bargagli-Stoffi ◽  
E. Amirante ◽  
J. Fischer ◽  
G. Iannaccone ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Cmos Technology ◽  
Power Supplies ◽  
Clock Generator ◽  
Optimum Frequency ◽  
Adiabatic Logic ◽  
Equivalent Load ◽  
Key Aspects ◽  
Multi Phase ◽  
Relationship Of ◽  
Phase Relationships

Abstract. Many adiabatic logic families make use of multi phase trapezoidal or sinusoidal power clocks to recover the energy stored in the load capacitances. A key aspect for the evaluation of the performance of adiabatic logic is then the study of a system that includes the power clock generator. A four-phase trapezoidal power clock generator, according to the requirements of the most promising architectures, namely the ECRL and PFAL, has been designed and simulated. The proposed circuit, realized with a double-well 0.25 µm CMOS technology and external inductors, is a resonant generator designed to oscillate at a frequency of 7 MHz, which is within the optimum frequency range for adiabatic circuits realized with this CMOS technology. The generator has been simulated with the equivalent load of fifty 1-bit adders and the operating behavior of a 4-bit adder has been evaluated. The key aspects of a generator for adiabatic logic are its power consumption and the phase relationships between its output signals. The proposed generator has a conversion efficiency higher than 80%, and it is robust with respect to variations of technology parameters. The four power supplies exhibit the correct relationship of phase also in the presence of no equally distributed loads.

scholarly journals 2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator

2006 ◽  
Vol 4 ◽  
pp. 287-291
Author(s):  
S. Tontisirin ◽  
R. Tielert
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Data Recovery ◽  
Voltage Controlled Oscillator ◽  
Clock Generator ◽  
Low Jitter ◽  
Phase Clock ◽  
Multi Phase ◽  
Frequency Detector

Abstract. A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1–2.25 Gb/s. Measurement of Bit-Error Rate is less than 10−12 for 2.25 Gb/s incoming data 27−1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.

scholarly journals Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY

2021 ◽  
Vol 2083 (2) ◽  
pp. 022032
Author(s):  
Yongzheng Zhan ◽  
Tuo Li ◽  
Yuqiu Yue ◽  
Tongqiang Liu ◽  
Yulong Zhou ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Hierarchical Architecture ◽  
Total Power ◽  
Cmos Inverter ◽  
High Data ◽  
Phase Stabilization ◽  
Noise Simulation ◽  
One Step ◽  
Multi Phase ◽  
Transmission Speed

Abstract A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.

scholarly journals A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1113 ◽  
Author(s):  
Heejae Hwang ◽  
Jongsun Kim
Keyword(s):  
Power Consumption ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
High Energy ◽  
Frequency Multiplication ◽  
Delay Locked Loop ◽  
Phase Interpolator ◽  
Linear Equalizer ◽  
Constant Output ◽  
Multi Phase

A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase reference clocks, which achieves multi-phase frequency multiplication with a small area and less power consumption. The shared MDLL generates and distributes eight-phase clocks to each CDR. The proposed CDR uses a new initial phase tracker that uses a preamble to achieve a fast lock time of about 12 ns and to provide a constant output data sequence. The CDR utilizes quarter-rate 2x-oversampling architecture, and the PI controller is designed full custom to minimize the loop latency. To improve the dithering jitter performance of the recovered clock, the decimation factor of the CDR can be adjustable. Also, a new continuous-time linear equalizer (CTLE) receiver was adopted to reduce power consumption and achieved a data rate of 25 Gb/s/lane. The proposed SerDes receiver with a digital CDR is implemented in 40 nm CMOS technology. The 100 Gb/s four-channel SerDes receiver (4 CTLEs + 4 CDRs + MDLL) occupies an active area of only 0.351 mm2 and consumes 241.8 mW, which achieves a high energy efficiency of 2.418 pJ/bit.

Some Applications of the U. S. Steel MVEM

1973 ◽  
Vol 31 ◽  
pp. 4-5
Author(s):  
J. S. Lally ◽  
L. E. Thomas ◽  
R. M. Fisher
Keyword(s):  
Electron Diffraction ◽  
Debye Temperature ◽  
Metals And Alloys ◽  
Critical Voltage ◽  
Dynamical Diffraction ◽  
Phase Structures ◽  
Structure Factors ◽  
Local Bonding ◽  
Diffraction Phenomenon ◽  
Multi Phase

A variety of materials containing many different microstructures have been examined with the USS MVEM. Three topics have been selected to illustrate some of the more recent studies of diffraction phenomena and defect, grain and multi-phase structures of metals and minerals.(1) Critical Voltage Effects in Metals and Alloys - This many-beam dynamical diffraction phenomenon, in which some Bragg resonances vanish at certain accelerating voltages, Vc, depends sensitively on the spacing of diffracting planes, Debye temperature θD and structure factors. Vc values can be measured to ± 0.5% in the HVEM ana used to obtain improved extinction distances and θD values appropriate to electron diffraction, as well as to probe local bonding effects and composition variations in alloys.

Digital imaging and quantitative image analysis of polymer blends

1996 ◽  
Vol 54 ◽  
pp. 170-171
Author(s):  
Xiao Zhang
Keyword(s):  
Digital Imaging ◽  
Imaging Techniques ◽  
Imaging Systems ◽  
Polymer Science ◽  
Key Factors ◽  
Multiple Imaging ◽  
Quantitative Image ◽  
Digital Imaging Systems ◽  
Multi Phase ◽  
Network Technologies

Polymer microscopy involves multiple imaging techniques. Speed, simplicity, and productivity are key factors in running an industrial polymer microscopy lab. In polymer science, the morphology of a multi-phase blend is often the link between process and properties. The extent to which the researcher can quantify the morphology determines the strength of the link. To aid the polymer microscopist in these tasks, digital imaging systems are becoming more prevalent. Advances in computers, digital imaging hardware and software, and network technologies have made it possible to implement digital imaging systems in industrial microscopy labs.

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