Combiner Networks for High Speed, High Density Integrated Circuit Susceptibility Testing

1986 ◽  
Author(s):  
John K. Daher ◽  
John P. Rohrbaugh
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Susceptibility Testing ◽  
High Density

scholarly journals Wire Laying Methods as an Alternative to Multilayer PCB's

1984 ◽  
Vol 11 (2) ◽  
pp. 117-122
Author(s):  
G. Messner ◽  
P. Plonski ◽  
A. Martens
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Impedance Control ◽  
Vlsi Circuits ◽  
High Density ◽  
Large Numbers ◽  
Design And Manufacturing ◽  
Computer Based ◽  
Board Performance ◽  
Circuit Technology

The rapid growth of integrated circuit technology, culminating in VLSI circuits, is responsible for the proliferation of new, surface mountable device packages with large numbers of input-output terminals. Conventional printed circuit or multilayer techniques have been driven to the technological edge in the effort to interconnect these new types of packages. Because the etched conductors can be replaced with fine, insulated wires, automated high density discrete wiring techniques can provide easier high density interconnections and with shorter turn-around times. Among the dozen or so presently available discrete wiring techniques, the fastest growing is Multiwire®. Multiwire is a computer based design and manufacturing system, where special machines are precisely laying down polyimide insulated wires over adhesive coated substrates having etched power and ground planes. The finished boards exhibit microstrip characteristics, providing impedance control for high speed applications. The manufacturing process and Multiwire board performance capabilities are described in this paper.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

Development of ATC for High Speed and High Density Commuter Line

2007 ◽  
Vol 127 (10) ◽  
pp. 1033-1042
Author(s):  
Tamio Okutani ◽  
Nobuyuki Nakamura ◽  
Hisato Araki ◽  
Shouji Irie ◽  
Hiroki Osa ◽  
...  
Keyword(s):  
High Speed ◽  
High Density

The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

A flexible gate array for high speed and high density applications

2002 ◽  
Author(s):  
J. Gallia ◽  
R. Landers ◽  
Ching-Hao Shaw ◽  
T. Blake ◽  
W. Banzhaf
Keyword(s):  
High Speed ◽  
High Density ◽  
Gate Array

Aluminum Reflow Sputtering

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 53-56 ◽  
Author(s):  
Kuniko Kikuta
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Lower Cost ◽  
High Reliability ◽  
Device Fabrication ◽  
Damascene Process ◽  
Aspect Ratios ◽  
Multi Level ◽  
Poor Adhesion ◽  
Lower Resistivity

The scaling of integrated-circuit device dimensions in the horizontal direction has caused an increase in aspect ratios of contact holes and vias without a corresponding scaledown in vertical dimensions. Conventional sputtering has become unreliable for handling higher aspect-ratio via/contact holes because of its poor step coverage. Several studies have attempted to overcome this problem by using W-CVD and reflow technology. The W-CVD is used for practical device fabrications. However, this technique has several problems such as poor adhesion to SiO2, poor W surface morphology, greater resistivity than Al, and the need of an etch-back process.Al reflow technology using a conventional DC magnetron sputtering system can simplify device-fabrication processes and achieve high reliability without Al/W interfaces. In particular, the Al reflow technology is profitable for multi-level interconnections in combination with a damascene process by using Al chemical mechanical polishing (CMP). These interconnections are necessary for miniaturized and high-speed devices because they provide lower resistivity than W and simplify fabrication processes, resulting in lower cost.This article describes recent Al reflow sputtering technologies as well as application of via and interconnect metallization.

scholarly journals A New CDS Structure for High Density FPA with Low Power

VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Xiao Wang ◽  
Zelin Shi
Keyword(s):  
Integrated Circuit ◽  
Dominant Role ◽  
Noise Analysis ◽  
Calculation Model ◽  
High Density ◽  
Integration Time ◽  
Subthreshold Region ◽  
Readout Integrated Circuit ◽  
Long Wave ◽  
Layout Area

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

Sign in / Sign up

Export Citation Format

Share Document