In-Situ predictive endpoint for dual damascene trench etch depth control for composite dielectric films

2004 ◽  
Author(s):  
R. Jaiswal ◽  
I. Sim ◽  
A. Jain ◽  
T.Q. Chen ◽  
L. Meng ◽  
...  
Keyword(s):  
Dielectric Films ◽  
Etch Depth ◽  
Dual Damascene ◽  
Depth Control

Atomic layer sensitive in-situ plasma etch depth control with reflectance anisotropy spectroscopy (RAS)

2017 ◽  
Author(s):  
Christoph Doering ◽  
Ann-Kathrin Kleinschmidt ◽  
Lars Barzen ◽  
Johannes Strassner ◽  
Henning Fouckhardt
Keyword(s):  
Atomic Layer ◽  
Etch Depth ◽  
Plasma Etch ◽  
Reflectance Anisotropy ◽  
Depth Control

scholarly journals Precise in situ etch depth control of multilayered III−V semiconductor samples with reflectance anisotropy spectroscopy (RAS) equipment

2016 ◽  
Vol 7 ◽  
pp. 1783-1793 ◽  
Author(s):  
Ann-Kathrin Kleinschmidt ◽  
Lars Barzen ◽  
Johannes Strassner ◽  
Christoph Doering ◽  
Henning Fouckhardt ◽  
...  
Keyword(s):  
Secondary Ion Mass Spectrometry ◽  
Semiconductor Device ◽  
Device Fabrication ◽  
Etch Depth ◽  
Reflectance Anisotropy ◽  
Depth Control ◽  
Dry Etch ◽  
First Time ◽  
Secondary Ion

Reflectance anisotropy spectroscopy (RAS) equipment is applied to monitor dry-etch processes (here specifically reactive ion etching (RIE)) of monocrystalline multilayered III–V semiconductors in situ. The related accuracy of etch depth control is better than 16 nm. Comparison with results of secondary ion mass spectrometry (SIMS) reveals a deviation of only about 4 nm in optimal cases. To illustrate the applicability of the reported method in every day settings for the first time the highly etch depth sensitive lithographic process to form a film lens on the waveguide ridge of a broad area laser (BAL) is presented. This example elucidates the benefits of the method in semiconductor device fabrication and also suggests how to fulfill design requirements for the sample in order to make RAS control possible.

The Formation of an Epitaxial-Graphene Cap Layer for Post-Implantation High Temperature Annealing of SiC and its In Situ Removal by Si-Vapor Etching

2011 ◽  
Vol 679-680 ◽  
pp. 777-780 ◽  
Author(s):  
Shoji Ushio ◽  
Ayumu Adachi ◽  
Kazuhiro Matsuda ◽  
Noboru Ohtani ◽  
Tadaaki Kaneko
Keyword(s):  
High Temperature ◽  
Graphene Layer ◽  
Treatment Method ◽  
Etch Depth ◽  
High Temperature Annealing ◽  
Large Area ◽  
Vapor Flux ◽  
Precise Control ◽  
Post Implantation

As a new graphene functionality applicable to post-implantation high temperature annealing of SiC, a method of in situ formation and removal of large area epitaxial few-layer graphene on 4H-SiC(0001) Si-face is proposed. It is demonstrated that the homogeneous graphene layer formed by Si sublimation can be preserved without the decomposition of the underlying SiC substrate even in the excess of 2000 oC in ultrahigh vacuum. It is due to the existence of the stable (6√3×6√3) buffer layer at the interface. To ensure this cap function, the homogeneity of the interface must be guaranteed. In order to do that, precise control of the initial SiC surface flatness is required. Si-vapor etching is a simple and versatile SiC surface pre/post- treatment method, where thermally decomposed SiC surface is compensated by a Si-vapor flux from Si solid source in the same semi-closed TaC container. While this Si-vapor etching allows precise control of SiC etch depth and surface step-terrace structures, it also provides a “decap” function to remove of the graphene layer. The surface properties after the each process were characterized by AFM and Raman spectroscopy.

Removing the Barriers to Next Generation'S Dielectric Films: In Situ Void-Free Planarized Films

1990 ◽  
Vol 203 ◽  
Author(s):  
J.R. Monkowski ◽  
M.A. Logan ◽  
L.F. Wright
Keyword(s):  
Aspect Ratio ◽  
Ion Chromatography ◽  
Field Measurements ◽  
Dielectric Films ◽  
Breakdown Field ◽  
Scanning Electron Micrographs ◽  
Aspect Ratios ◽  
New Process ◽  
Scanning Electron

ABSTRACTIn the next generation of semiconductor devices, minimum dimensions will be smaller, aspect ratios (height to width) of devices features will be larger, and BPSG dielectrics will be challenged to deal with these changes. A new process, which integrates deposition, flow, and anneal of BPSG films, and allows void-free filling of high-aspect-ratio trenches with excellent surface planarization, is presented in this paper. Scanning electron micrographs are used to show the extent of film coverage and planarization. Additional characterization includes ion chromatography, ellipsometry, stress measurements, and breakdown field measurements.

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