A 28–34 GHz Stacked-FET Power Amplifier in 28-nm FD-SOI with Adaptive Back-gate Control for Improving Linearity

With the ongoing race to deploy the fifth generation of wireless technologies, the research is directed towards the millimeter wave carrier frequencies as a result of the demand for high speed data and the need for more spectrum bandwidth. Beside the large bandwidth, one of the major challenges of the 5G is reducing energy consumption. The power amplifier is the most critical element of the radiofrequency front-end in terms of power consumption and bandwidth. In this work, we present the design of a wideband and highly efficient class J power amplifier. Post-layout simulation results show a broadband behavior over 12 GHz of bandwidth, with a power added efficiency of 38 % and a saturated output power of 16.2 dBm at 28 GHz. In addition, the linearity and the efficiency of the power amplifier are reconfigurable with to the back-gate of the 28 nm CMOS FD-SOI technology.

Download Full-text

Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Journal of Electronic Materials ◽

10.1007/s11664-017-5508-7 ◽

2017 ◽

Vol 46 (8) ◽

pp. 5046-5056

Author(s):

Gopi Krishna Saramekala ◽

Pramod Kumar Tiwari

Keyword(s):

Subthreshold Swing ◽

Back Gate ◽

Fully Depleted ◽

Soi Mosfet ◽

Subthreshold Current ◽

Gate Control

Download Full-text

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078720001087 ◽

2020 ◽

pp. 1-18

Author(s):

Florent Torres ◽

Eric Kerhervé ◽

Andreia Cathelin ◽

Magali De Matos

Keyword(s):

Power Amplifier ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Fully Depleted ◽

Technology Roadmap ◽

Wide Range ◽

28 Nm ◽

Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

Download Full-text

A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽

10.3390/electronics8010069 ◽

2019 ◽

Vol 8 (1) ◽

pp. 69 ◽

Cited By ~ 3

Author(s):

Taufiq Alif Kurniawan ◽

Toshihiko Yoshimasu

Keyword(s):

Power Amplifier ◽

High Efficiency ◽

Low Voltage ◽

Supply Voltage ◽

Drain Current ◽

Cmos Technology ◽

Back Gate ◽

Third Harmonic ◽

Power Added Efficiency ◽

Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

Download Full-text