Analysis of Capacitances in Asymmetric Self-Cascode SOI nMOSFETs

2021 ◽  
Author(s):  
Camila Restani Alves ◽  
Ligia Martins d'Oliveira ◽  
Michelly de Souza
Keyword(s):  
Self Cascode

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals Self-Cascode Current-Voltage Curve-Construction Algorithm from Single MOSFET Measurements for Analog Figures-of-Merit Extraction

2019 ◽  
Vol 14 (1) ◽  
pp. 1-6
Author(s):  
Li�gia Martins d'Oliveira ◽  
Valeriya Kilchytska ◽  
Denis Flandre ◽  
Michelly De Souza
Keyword(s):  
Threshold Voltage ◽  
Extraction Method ◽  
New Technologies ◽  
Experimental Measurements ◽  
Saturation Regime ◽  
Figures Of Merit ◽  
Voltage Curve ◽  
Current Voltage ◽  
Current Voltage Curve ◽  
Self Cascode

This paper proposes a curve extraction method for I-V curves and analog figures-of-merit of self-cascode MOSFET associations (SC) using a code that exploits I-V curves of single transistors as input. The method was validated by using experimental measurements of fabricated SC and the very single transistors that compose them. The results indicate a very low error between the SC generated by the code and the measured reference for operation in saturation regime and above threshold voltage, for both the I-V curves and their derivatives. This method is then valid for the assessment of the SC structures in new technologies, avoiding experimental dedicated layouts or complex set-ups.

Reconfigurable low voltage low power dual-band self-cascode current-reuse quasi-differential LNA for 5G

2019 ◽  
Vol 92 ◽  
pp. 104602 ◽  
Author(s):  
K. Hari Kishore ◽  
V. Senthil Rajan ◽  
R. Sanjay ◽  
B. Venkataramani
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Dual Band ◽  
Current Reuse ◽  
Self Cascode

Self-Cascode MOSFET with a Self-Biased Body Effect for Ultra-Low-Power Voltage Reference Generator

2013 ◽  
Vol E96.C (6) ◽  
pp. 859-866
Author(s):  
Hao ZHANG ◽  
Mengshu HUANG ◽  
Yimeng ZHANG ◽  
Tsutomu YOSHIHARA
Keyword(s):  
Low Power ◽  
Voltage Reference ◽  
Body Effect ◽  
Ultra Low Power ◽  
Reference Generator ◽  
Self Cascode

scholarly journals CMOS Voltage Reference using a Self-Cascode Composite Transistor and a Schottky Diode

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary
Keyword(s):  
Schottky Diode ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Silicon Area ◽  
Circuit Topology ◽  
Voltage Range ◽  
Self Cascode ◽  
Cmos Voltage Reference ◽  
The Impact

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.

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