Design of conventional three-stage CMOS comparator in 90-nm CMOS technology and comparative analysis with its counterparts

2015 ◽  
Author(s):  
Satyabrata Nanda ◽  
Avipsa S. Panda
Keyword(s):  
Comparative Analysis ◽  
Cmos Technology

scholarly journals A Comparative Study of 6T and 8T SRAM Cell With Improved Read and Write Margins in 130 nm CMOS Technology

2020 ◽  
Vol 19 ◽  
Keyword(s):  
Comparative Analysis ◽  
Random Access ◽  
Cmos Technology ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Random Access Memories ◽  
Node Voltage ◽  
Improve Stability ◽  
Static Noise ◽  
Better Than

This paper examines the factors that affect the Static Noise Margin (SNM) of a Static Random Access memories which focus on optimizing Read and Write operation of 8T SRAM cell which is better than 6T SRAM cell Using Swing Restoration for Dual Node Voltage. The read and Write time and improve Stability. New 8T SRAM technique on the circuit or architecture level is required. In this paper Comparative Analysis of 6T and 8T SRAM Cells with Improved Read and Write Margin is done for 130 nm Technology with Cadence Virtuoso schematics Tool.

scholarly journals A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

2019 ◽  
Vol 8 (11S) ◽  
pp. 11-19
Keyword(s):  
Comparative Analysis ◽  
High Resolution ◽  
Low Power ◽  
Time Domain ◽  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

CNTFET-Based Ternary Logic Gates

2020 ◽  
pp. 72-92
Author(s):  
Suman Rani ◽  
Balwinder Singh
Keyword(s):  
Energy Efficiency ◽  
Comparative Analysis ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Logic Gates ◽  
Cmos Technology ◽  
Nand Gate ◽  
Ternary Logic ◽  
Average Delay ◽  
Universal Gates

In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.

Sign in / Sign up

Export Citation Format

Share Document