Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology

2020 ◽  
Author(s):  
Vaibhav Verma ◽  
Fiza Akhtar ◽  
Anuj Grover
Keyword(s):  
Comparative Analysis ◽  
Cmos Technology ◽  
Sense Amplifier

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

2012 ◽  
Vol 542-543 ◽  
pp. 769-774
Author(s):  
Qun Ling Yu ◽  
Na Bai ◽  
Yan Zhou ◽  
Rui Xing Li ◽  
Jun Ning Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Optimal Operation ◽  
Reduction Technique ◽  
Total Speed ◽  
Sense Amplifier ◽  
Simulation Results ◽  
A New Technique ◽  
Total Energy Dissipation

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

LOW POWER AND HIGH PERFORMANCE SINGLE-ENDED SENSE AMPLIFIER

2013 ◽  
Vol 22 (07) ◽  
pp. 1350062 ◽  
Author(s):  
AJAY KUMAR SINGH ◽  
MAH MENG SEONG ◽  
C. M. R. PRABHU
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Voltage Drop ◽  
Cmos Technology ◽  
Power Efficient ◽  
Sense Amplifier ◽  
Current Voltage ◽  
Direct Current Voltage ◽  
Voltage Conversion ◽  
Lower Voltage

This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation.

scholarly journals A Comparative Study of 6T and 8T SRAM Cell With Improved Read and Write Margins in 130 nm CMOS Technology

2020 ◽  
Vol 19 ◽  
Keyword(s):  
Comparative Analysis ◽  
Random Access ◽  
Cmos Technology ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Random Access Memories ◽  
Node Voltage ◽  
Improve Stability ◽  
Static Noise ◽  
Better Than

This paper examines the factors that affect the Static Noise Margin (SNM) of a Static Random Access memories which focus on optimizing Read and Write operation of 8T SRAM cell which is better than 6T SRAM cell Using Swing Restoration for Dual Node Voltage. The read and Write time and improve Stability. New 8T SRAM technique on the circuit or architecture level is required. In this paper Comparative Analysis of 6T and 8T SRAM Cells with Improved Read and Write Margin is done for 130 nm Technology with Cadence Virtuoso schematics Tool.

scholarly journals Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

2019 ◽  
Vol 9 (1S3) ◽  
pp. 85-89
Keyword(s):  
Dead Zone ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Sense Amplifier ◽  
Time Amplifier ◽  
Frequency Detector ◽  
Cmos Implementation

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

scholarly journals Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

2014 ◽  
Vol 68 (3) ◽  
Author(s):  
Nor Zaidi Haron ◽  
Norsuhaidah Arshad ◽  
Fauziyah Salehuddin
Keyword(s):  
Performance Analysis ◽  
Defect Density ◽  
Random Access ◽  
Cmos Technology ◽  
Resistive Random Access Memory ◽  
Cell Array ◽  
Access Memory ◽  
Sense Amplifier ◽  
Emerging Memory ◽  
Initial Work

Resistive Random Access Memory (RRAM) is gaining attention as one of the prominent contenders to replace the conventional memory technologies such as SRAM, DRAM and Flash. This emerging memory uses scaled CMOS devices (22 nm or less) to form the peripheral circuits such as decoder and sense amplifier; while a non-CMOS device known as memristor is used to form the cell array. Although potentially becoming the main future memory, RRAM is anticipated to be impacted by the high manufacturing defect density that in turn might lead to quality and reliability problems. This paper presents the initial work towards producing a high quality and reliable RRAM devices. A design and simulation of three memristor SPICE models published in prominent literatures were performed using Silvaco EDA simulation tool. The aim is to identify the optimal model to be used in our RRAM design, which is based on 22 nm CMOS technology. Performance analysis shows that the model proposed by D. Biolek is suitable to be used in our RRAM design.

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