Junction Temperature Prediction of the Multi-LED Module with the Modified Thermal Resistance Matrix

2019 ◽  
Author(s):  
Fanny Zhao ◽  
Brian Shieh ◽  
Fangyun Zeng ◽  
Guoming Yang ◽  
S. W. Ricky Lee
Keyword(s):  
Thermal Resistance ◽  
Junction Temperature ◽  
Temperature Prediction ◽  
Resistance Matrix

scholarly journals Influence of a Thermal Pad on Selected Parameters of Power LEDs

Energies ◽  
2020 ◽  
Vol 13 (14) ◽  
pp. 3732
Author(s):  
Krzysztof Górecki ◽  
Przemysław Ptak ◽  
Tomasz Torzewicz ◽  
Marcin Janicki
Keyword(s):  
Optical Properties ◽  
Thermal Resistance ◽  
Optical Power ◽  
Junction Temperature ◽  
Operating Parameters ◽  
Cold Plate ◽  
Optical Efficiency ◽  
Forward Current ◽  
Measurement Results ◽  
Set Up

This paper is devoted to the analysis of the influence of thermal pads on electric, optical, and thermal parameters of power LEDs. Measurements of parameters, such as thermal resistance, optical efficiency, and optical power, were performed for selected types of power LEDs operating with a thermal pad and without it at different values of the diode forward current and temperature of the cold plate. First, the measurement set-up used in the paper is described in detail. Then, the measurement results obtained for both considered manners of power LED assembly are compared. Some characteristics that illustrate the influence of forward current and temperature of the cold plate on electric, thermal, and optical properties of the tested devices are presented and discussed. It is shown that the use of the thermal pad makes it possible to achieve more advantageous values of operating parameters of the considered semiconductor devices at lower values of their junction temperature, which guarantees an increase in their lifetime.

Approximate Analytical Model for a First Level Package With Non-Uniformly Powered Die

2006 ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Thermal Resistance ◽  
Analytical Model ◽  
Functional Integration ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Design Guideline ◽  
Functional Blocks ◽  
Distribution Of Power ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.

Integration of Silver Heat Spreaders in LTCC utilizing Thick Silver Tape in the Co-fire Process

2015 ◽  
Vol 2015 (CICMT) ◽  
pp. 000062-000066 ◽  
Author(s):  
T. Welker ◽  
S. Günschmann ◽  
N. Gutzeit ◽  
J. Müller
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Heat Sink ◽  
Junction Temperature ◽  
Large Area ◽  
Heat Spreader ◽  
Integration Density ◽  
Heat Spreaders ◽  
Cte Mismatch ◽  
Pattern Resolution

The integration density in semiconductor devices is significantly increased in the last years. This trend is already described by Moore's law what forecasts a doubling of the integration density every two years. This evolution makes greater demands on the substrate technology which is used for the first level interconnect between the semiconductor and the device package. Higher pattern resolution is required to connect more functions on a smaller chip. Also the thermal performance of the substrate is a crucial issue. The increased integration density leads to an increased power density, what means that more heat has to dissipate on a smaller area. Thus, substrates with a high thermal conductivity (e. g. direct bonded copper (DBC)) are utilized which spread the heat over a large area. However, the reduced pattern resolution caused by thick metal layers is disadvantageous for this substrate technology. Alternatively, low temperature co-fired ceramic (LTCC) can be used. This multilayer technology provides a high pattern resolution in combination with a high integration grade. The poor thermal conductivity of LTCC (3 … 5 W*m−1*K−1) requires thermal vias made of silver paste which are placed between the power chip and the heat sink and reduce the thermal resistance of the substrate. The via-pitch and diameter is limited by the LTCC technology, what allows a maximum filling grade of approx. 20 to 25 %. Alternatively, an opening in the ceramic is created, to bond the chip directly to the heat sink. This leads to technological challenges like the CTE mismatch between the chip and the heat sink material. Expensive materials like copper molybdenum composites with matched CTE have to be used. In the presented investigation, a thick silver tape is used to form a thick silver heat spreader through the LTCC substrate. An opening is structured by laser cutting in the LTCC tape and filled with a laser cut silver tape. After lamination, the substrate is fired using a constraint sintering process. The bond strength of the silver to LTCC interface is approx. 5.6 MPa. The thermal resistance of the silver structure is measured by a thermal test chip (Delphi PST1, 2.5 mm × 2.5 mm) glued with a high thermal conducting epoxy to the silver structure. The chip contains a resistor and diodes to generate heat and to determine the junction temperature respectively. The backside of the test structure is temperature stabilized by a temperature controlled heat sink. The resulting thermal resistance is in the range of 1.1 K/W to 1.5 K/W depending on the length of silver structure (5 mm to 7 mm). Advantages of the presented heat spreader are the low thermal resistance and the good embedding capability in the co-fire LTCC process.

An Investigation Into the Potential of Low-Reynolds Number Eddy Viscosity Turbulent Flow Models to Predict Electronic Component Operational Temperature

2005 ◽  
Vol 127 (1) ◽  
pp. 67-75 ◽  
Author(s):  
Peter Rodgers ◽  
Vale´rie Eveloy ◽  
M. S. J. Hashmi
Keyword(s):  
Thermal Analysis ◽  
Reynolds Number ◽  
Eddy Viscosity ◽  
Predictive Accuracy ◽  
Low Reynolds Number ◽  
Turbulence Models ◽  
Thermal Design ◽  
Junction Temperature ◽  
Temperature Prediction ◽  
Low Reynolds

The flow modeling approaches employed in computational fluid dynamics (CFD) codes dedicated to the thermal analysis of electronic equipment are generally not specific for the analysis of forced airflows over populated electronic boards. This limitation has been previously highlighted (Eveloy, V. et al., 2004, IEEE Trans. Compon., Packag., Technol. 27, pp. 268–282), with component junction temperature prediction errors of up to 35% reported. This study evaluates the potential of three candidate low-Reynolds number eddy viscosity turbulence models to improve predictive accuracy. An array of fifteen board-mounted PQFPs is analyzed in a 4 m/s airflow. Using the shear stress transport k-ω model, significant improvements in component junction temperature prediction accuracy are obtained relative to the standard high-Reynolds number k-ε model, which are attributed to better prediction of both board leading edge heat transfer and component thermal interaction. Such improvements would enable parametric analysis of product thermal performance to be undertaken with greater confidence in the thermal design process, and the generation of more accurate temperature boundary conditions for use in Physics-of-Failure based reliability prediction methods. The case is made for vendors of CFD codes dedicated to the thermal analysis of electronics to consider the adoption of eddy viscosity turbulence models more suited to board-level analysis.

scholarly journals Analysis and Prediction of Thermal Resistance for High Power LED Using GA-SVR

2012 ◽  
Vol 4 ◽  
pp. 153-160
Author(s):  
De Huai Zeng ◽  
Yuan Liu ◽  
Li Li ◽  
De Gui Yu ◽  
Gang Xu
Keyword(s):  
Service Life ◽  
Thermal Resistance ◽  
High Power ◽  
Thermal Characteristics ◽  
Junction Temperature ◽  
Support Vector ◽  
Mean Squared Errors ◽  
Absolute Relative Error ◽  
High Power Led ◽  
Key Factor

With the development of high power LED technology, junction temperature as a key factor constrains the performance and the service life of LED, and the main parameter of junction temperature is thermal resistance. Therefore, how to measure the thermal resistance of high power LED quickly and accurately plays an important part in improving the performance and the service life of LED. In this paper the accurate and fast measurement equipment was applied to study the thermal characteristics of high power LED. The forward-voltage based method was conducted to measure the junction temperature of high power. Then, support vector regression (SVR) combined with genetic algorithm (GA) for its parameter optimization, was proposed to establish a model to predict the thermal resistance of high power LED. The prediction performance of GA-SVR was compared with those of BPNN model. The result demonstrated that the estimated errors GA-SVR models, such as Mean Absolute Relative Error (MARE) and Root Mean Squared Errors (RMSE), all are smaller than those achieved by the BPNN applying identical samples.

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