Approximate Analytical Model for a First Level Package With Non-Uniformly Powered Die

2006 ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Thermal Resistance ◽  
Analytical Model ◽  
Functional Integration ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Design Guideline ◽  
Functional Blocks ◽  
Distribution Of Power ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.

Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die

2005 ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Heat Flux ◽  
Functional Integration ◽  
Design Guidelines ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Chip Surface ◽  
Functional Block ◽  
Functional Blocks ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.

Development of an Analytical Model to a Temperature Distribution of First Level Package With a Non-Uniformly Powered Die

2007 ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Heat Flux ◽  
Temperature Distribution ◽  
Analytical Model ◽  
Functional Integration ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Uniform Heat Flux ◽  
Chip Surface ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work has been done which includes numerical analysis and thermal Based optimization of a typical package consisting of a non-uniformly powered die, heat spreader, TIM I &II and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a non-uniformly powered die is carried out for the first time. The analytical model for two layer bodies developed by Haji-Sheikh et al. is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology will be applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution will be carried out using developed numerical model.

Development of Analytical Model to a Temperature Distribution of a First Level Package With a Nonuniformly Powered Die

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Heat Flux ◽  
Temperature Distribution ◽  
San Francisco ◽  
Analytical Model ◽  
Functional Integration ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Functional Block ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity, and performance. Microprocessors typically integrate functional components such as logic and level two cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly nonuniform, and the assumption of a uniform heat flux across the die surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work (Kaisare et al., 2005, “Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die,” InterPACK 2005, San Francisco, CA, Jul. 17–22) has been done, which includes numerical analysis and thermal based optimization of a typical package consisting of a nonuniformly powered die, heat spreader, thermal interface materials I and II, and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a nonuniformly powered die is carried out for the first time. The analytical model for two-layer bodies developed by Haji-Sheikh et al. (2003, “Steady-State Heat Conduction in Multi-Layer Bodies,” Int. J. Heat Mass Transfer, 46(13), pp. 2363–2379) is extended to this typical package, which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology is applied to solve the equations for various surfaces to calculate the maximum junction temperature for a given multilayer body. Finally validation of the analytical solution is carried out using previously developed numerical model.

scholarly journals A Comparative Study of Silicon Carbide Merged PiN Schottky Diodes with Electrical-Thermal Coupled Considerations

Materials ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2669
Author(s):  
Jiupeng Wu ◽  
Na Ren ◽  
Qing Guo ◽  
Kuang Sheng
Keyword(s):  
Silicon Carbide ◽  
Comparative Study ◽  
Thermal Resistance ◽  
Heat Dissipation ◽  
Schottky Diodes ◽  
Layout Design ◽  
Thermal Design ◽  
Junction Temperature ◽  
Bipolar Conduction ◽  
Surge Current

A comparative study of surge current reliability of 1200 V/5 A 4H-SiC (silicon carbide) MPS (Merged PiN Schottky) diodes with different technologies is presented. The influences of device designs in terms of electrical and thermal aspects on the forward conduction performance and surge current capability were studied. Device forward characteristics were simulated and measured. Standard single-pulse surge current tests and thermal impedance measurements were carried to show their surge capability and thermal design differences. An advanced thermal RC (thermal resistance-capacitance) model, with the consideration of current distribution non-uniformity effects, is proposed to accurately calculate the device junction temperature during surge events. It was found that a thinner substrate and a hexagonal layout design are beneficial to the improvement of the bipolar conduction performance in high current mode, as well as the surge current capability. The thinner substrate design also has advantages on thermal aspects, as it presents the lowest thermal resistance. The calculated failure temperature during the surge tests is consistent with the aluminum melting phenomenon, which is regarded as the failure mechanism. It was demonstrated that, for a SiC MPS diode, higher bipolar conduction performance is conducive to restraining the joule heat, and a lower thermal resistance design is able to accelerate the heat dissipation and limit the junction temperature during surge events. In this way, the MPS diode using a thinner substrate and advanced layout design technology is able to achieve 60% higher surge current density capability compared to the other technologies.

Development of a Numerical Model for Non-Uniformly Powered Die to Improve Both Thermal and Device Clock Performance

2009 ◽  
Author(s):  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Kanad Ghose ◽  
Bahgat Sammakia ◽  
Cristina Amon ◽  
...  
Keyword(s):  
Power Distribution ◽  
High Speed ◽  
Junction Temperature ◽  
Total Power ◽  
Maximum Temperature ◽  
Large Temperature ◽  
Computer Performance ◽  
Performance Loss ◽  
Functional Blocks ◽  
Functional Components

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional blocks dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effect on computer performance and product reliability as well as yield. Moving the functional blocks may reduce the junction temperature but can also affect the performance by a factor as high as 35%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 82.4°C and 94.5°C with a corresponding penalty on the performance of 35% and 0% respectively. The optimized location of the functional blocks resulted in a temperature of 83.2°C for a performance loss of 5%.

Design of a Cold Plate Tester for Accurate Measurement of Thermal Performance

2005 ◽  
Author(s):  
Nikhil Lakhkar ◽  
Madhusudan Iyengar ◽  
Michael Ellsworth ◽  
Dereje Agonafer
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
High Performance ◽  
Heat Dissipation ◽  
Thermal Design ◽  
Junction Temperature ◽  
Cold Plate ◽  
Expected Performance ◽  
Cold Plates ◽  
Effective Heat Transfer Coefficient

With the continuing industry trends towards smaller, faster and higher power devices, thermal management has become an extremely important element in the development of computer products. The primary goal of a good thermal design is to ensure that the chip can function at its rated frequency, while maintaining its junction temperature below the specified limit, to ensure reliable operation. The use of a heat sink or cold plate to manage the external thermal resistance has been well documented in the literature. However, the measurement of thermal performance of today state-of-the-art cold plates is challenging because of the low value of thermal resistance that they offer to heat dissipation. In this paper, the design of a tester apparatus for such high performance cold plates is presented. The expected performance of the tester is modeled numerically for a heat flux of 250 W/cm2, and for a range of footprint areas of 100-400 mm2. The analysis study is supported by a detailed uncertainty analysis that utilizes a Monte Carlo simulation approach. It was observed that the sum of random and repeatable errors could be controlled to within ±7.5% even for a very high performance cold plate with an effective heat transfer coefficient of 200,000 W/m2-K dissipating 250 W/cm2, with assumed errors in other relevant parameters.

scholarly journals Development of Analytical Model for a Vertical Single U-Tube Ground-Coupled Heat Pump System

2020 ◽  
pp. 1-14
Author(s):  
Ali H. Tarrad
Keyword(s):  
Thermal Resistance ◽  
Analytical Model ◽  
Heat Pump ◽  
Diameter Ratio ◽  
Thermal Design ◽  
Pump System ◽  
Heat Pump System ◽  
Ground Heat Exchangers ◽  
Borehole Thermal Resistance ◽  
Outside Diameter

An analytical model was built to study the thermal design of a single vertical U-tube coupled heat pump under steady-state conditions. It was based on the philosophy of U-tube replacement by an equivalent thermal resistance situated between the heat transfer medium that flows inside the tube and the borehole boundary. An obstruction factor was introduced to account for the reduction of heat flow from or to a tube in the borehole due to the presence of the second leg of the U-tube. Two Copper U-tubes with wall factors of (12.5) and (14.29) were implemented to comprise several borehole configurations to verify the present work. The shank spacing was ranged between (2) and (4) times the U-tube outside diameter producing shank spacing to borehole diameter ratio range of (0.29-0.59). The model was utilized for the assessment of DX ground heat exchangers works as a condenser for cooling purposes. Reducing of the tube spacing to tube outside diameter ratio from (3.3) to (2) for both tube wall factors showed a rise for the borehole thermal resistance in the range of (22-54)% and (26.5-28)% predicted at wall factors of (12.5) and (14.29) respectively.

scholarly journals Influence of a Thermal Pad on Selected Parameters of Power LEDs

Energies ◽  
2020 ◽  
Vol 13 (14) ◽  
pp. 3732
Author(s):  
Krzysztof Górecki ◽  
Przemysław Ptak ◽  
Tomasz Torzewicz ◽  
Marcin Janicki
Keyword(s):  
Optical Properties ◽  
Thermal Resistance ◽  
Optical Power ◽  
Junction Temperature ◽  
Operating Parameters ◽  
Cold Plate ◽  
Optical Efficiency ◽  
Forward Current ◽  
Measurement Results ◽  
Set Up

This paper is devoted to the analysis of the influence of thermal pads on electric, optical, and thermal parameters of power LEDs. Measurements of parameters, such as thermal resistance, optical efficiency, and optical power, were performed for selected types of power LEDs operating with a thermal pad and without it at different values of the diode forward current and temperature of the cold plate. First, the measurement set-up used in the paper is described in detail. Then, the measurement results obtained for both considered manners of power LED assembly are compared. Some characteristics that illustrate the influence of forward current and temperature of the cold plate on electric, thermal, and optical properties of the tested devices are presented and discussed. It is shown that the use of the thermal pad makes it possible to achieve more advantageous values of operating parameters of the considered semiconductor devices at lower values of their junction temperature, which guarantees an increase in their lifetime.

scholarly journals Novel Structure and Thermal Design and Analysis for CubeSats in Formation Flying

Aerospace ◽  
2021 ◽  
Vol 8 (6) ◽  
pp. 150
Author(s):  
Yeon-Kyu Park ◽  
Geuk-Nam Kim ◽  
Sang-Young Park
Keyword(s):  
Analytical Model ◽  
Formation Flying ◽  
Thermal Environment ◽  
Thermal Analyses ◽  
Thermal Design ◽  
Analytical Models ◽  
Test Results ◽  
Solar Panels ◽  
Novel Structure ◽  
Micro Propulsion

The CANYVAL-C (CubeSat Astronomy by NASA and Yonsei using a virtual telescope alignment for coronagraph) is a space science demonstration mission that involves taking several images of the solar corona with two CubeSats—1U CubeSat (Timon) and 2U CubeSat (Pumbaa)—in formation flying. In this study, we developed and evaluated structural and thermal designs of the CubeSats Timon and Pumbaa through finite element analyses, considering the nonlinearity effects of the nylon wire of the deployable solar panels installed in Pumbaa. On-orbit thermal analyses were performed with an accurate analytical model for a visible camera on Timon and a micro propulsion system on Pumbaa, which has a narrow operating temperature range. Finally, the analytical models were correlated for enhancing the reliability of the numerical analysis. The test results indicated that the CubeSats are structurally safe with respect to the launch environment and can activate each component under the space thermal environment. The natural frequency of the nylon wire for the deployable solar panels was found to increase significantly as the wire was tightened strongly. The conditions of the thermal vacuum and cycling testing were implemented in the thermal analytical model, which reduced the differences between the analysis and testing.

Thermal Design of a Satellite Borne FPGA

2011 ◽  
Vol 52-54 ◽  
pp. 1411-1414 ◽  
Author(s):  
Bo Chen
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Heat Sink ◽  
Thermal Design ◽  
Junction Temperature ◽  
Element Analysis

Thermal design and analysis of a satellite borne FPGA is described in this paper. Thermal-conductive glue, vias and an aluminum bar were used to the FPGA and the PCB under the FPGA in order to help conduct the heat of the FPGA to heat sink. The results of finite element analysis showed that the case temperature of the FPGA decreased from 132.5°C to 55.4°C and the junction temperature decreased from 136.1°C to59.0 °C after the thermal design, which matches the requirements of thermal design.

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