3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO2Hybrid Bonding

2014 ◽  
Vol 61 (8) ◽  
pp. 2886-2892 ◽  
Author(s):  
Masahide Goto ◽  
Kei Hagiwara ◽  
Yoshinori Iguchi ◽  
Hiroshi Ohtake ◽  
Takuya Saraya ◽  
...  
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.


Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.


2012 ◽  
Vol 195 ◽  
pp. 75-78
Author(s):  
Chung Kyung Jung ◽  
Sung Wook Joo ◽  
Seoung Hun Jeong ◽  
Sang Wook Ryu ◽  
Han Choon Lee ◽  
...  

Over the last decades, the concept of backside illumination (BSI) sensors has become one of the leading solutions to optical challenges such as improved quantum efficiency (QE), and cross-talk, respectively [1-. Direct wafer bonding is a method for fabricating advanced substrates for micro-electrochemical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer.


1997 ◽  
Vol 469 ◽  
Author(s):  
Guénolé C.M. Silvestre

ABSTRACTSilicon-On-Insulator (SOI) materials have emerged as a very promising technology for the fabrication of high performance integrated circuits since they offer significant improvement to device performance. Thin silicon layers of good crystalline quality are now widely available on buried oxide layers of various thicknesses with good insulating properties. However, the SOI structure is quite different from that of bulk silicon. This paper will discuss a study of point-defect diffusion and recombination in thin silicon layers during high temperature annealing treatment through the investigation of stacking-fault growth kinetics. The use of capping layers such as nitride, thin thermal oxide and thick deposited oxide outlines the diffusion mechanisms of interstitials in the SOI structure. It also shows that the buried oxide layer is a very good barrier to the diffusion of point defects and that excess silicon interstitials may be reincorporated at the top interface with the thermal oxide through the formation of SiO species. Finally, from the experimental values of the activation energies for the growth and the shrinkage of stacking-faults, the energy of interstitial creation is evaluated to be 2.6 eV, the energy for interstitial migration to be 1.8 eV and the energy of interstitial generation during oxidation to be 0.2 eV.


1992 ◽  
Vol 284 ◽  
Author(s):  
F. Namavar ◽  
B. Buchanan ◽  
N. M. Kalkhoran

ABSTRACTSilicon-on-insulator (SOI) wafers made by standard energy (150–200 keV) Separation by IMplantation of Oxygen (SIMOX) processes have shown great promise for meeting the needs of radiation-hard microelectronics. However, if SIMOX material is to become a competitive substrate material for manufacturing commercial integrated circuits, the cost of the SIMOX wafers must be greatly reduced. The low energy SIMOX (LES) process accomplishes the needed reduction in cost by producing ultrathin layers which require much lower ion doses. These ultrathin layers are necessary for the next generation of commercial ultra high density CMOS integrated circuits, and must be of very high quality to be utilized for commercial applications. In this paper we discuss characterization of ultrathin LES structures.


2001 ◽  
Vol 32 (5-6) ◽  
pp. 517-526 ◽  
Author(s):  
D.M Garner ◽  
F Udrea ◽  
H.T Lim ◽  
G Ensell ◽  
A.E Popescu ◽  
...  

1999 ◽  
Vol 46 (8) ◽  
pp. 1733-1741 ◽  
Author(s):  
G. Dambrine ◽  
J.-P. Raskin ◽  
F. Danneville ◽  
D. Vanhoenackel Janvier ◽  
J.-P. Colinge ◽  
...  

Author(s):  
W. Bogaerts ◽  
S.K. Selvaraja ◽  
P. Dumon ◽  
P. Absil ◽  
D. Van Thourhout ◽  
...  

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