scholarly journals Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

2016 ◽  
Vol 24 (5) ◽  
pp. 1739-1748 ◽  
Author(s):  
Daniel Arumi ◽  
Rosa Rodriguez-Montanes ◽  
Joan Figueras
Keyword(s):  
Leakage Currents ◽  
Open Faults ◽  
Test Escapes

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Comparison of Active and Passive Voltage Contrast for Failure Localization

2007 ◽  
Author(s):  
R. Rosenkranz ◽  
W. Werner
Keyword(s):  
Case Studies ◽  
Optical Beam ◽  
Leakage Currents ◽  
Localization Method ◽  
Voltage Contrast ◽  
Failure Localization

Abstract In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.

Thermal Laser Stimulation Technique for AlGaN/GaN HEMT Technologies Improvement

2013 ◽  
Author(s):  
Dominique Carisetti ◽  
Nicolas Sarazin ◽  
Nathalie Labat ◽  
Nathalie Malbert ◽  
Arnaud Curutchet ◽  
...  
Keyword(s):  
Surface States ◽  
Leakage Currents ◽  
Laser Stimulation ◽  
Long Term Stability ◽  
Field Plate ◽  
Gan Hemt ◽  
Die Surface ◽  
Scan Speed ◽  
Stimulation Technique

Abstract To improve the long-term stability of AlGaN/GaN HEMTs, the reduction of gate and drain leakage currents and electrical anomalies at pinch-off is required. As electron transport in these devices is both coupled with traps or surface states interactions and with polarization effects, the identification and localization of the preeminent leakage path is still challenging. This paper demonstrates that thermal laser stimulation (TLS) analysis (OBIRCh, TIVA, XIVA) performed on the die surface are efficient to localize leakage paths in GaN based HEMTs. The first part details specific parameters, such as laser scan speed, scan direction, wavelength, and laser power applied for leakage gate current paths identification. It compares results obtained with Visible_NIR electroluminescence analysis with the ones obtained by the TLS techniques on GaN HEMT structures. The second part describes some failure analysis case studies of AlGaN/GaN HEMT with field plate structure which were successful, thanks to the OBIRCh technique.

Fault Isolation of Open Defects Using Space Domain Reflectometry

2012 ◽  
Author(s):  
Mayue Xie ◽  
Zhiguo Qian ◽  
Mario Pacheco ◽  
Zhiyong Wang ◽  
Rajen Dias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Fault Isolation ◽  
Nondestructive Technique ◽  
Space Domain ◽  
New Approach ◽  
Defect Localization ◽  
Open Faults ◽  
Open Defects ◽  
Application Optimization ◽  
Rf Magnetic Field

Abstract Recently, a new approach for isolation of open faults in integrated circuits (ICs) was developed. It is based on mapping the radio-frequency (RF) magnetic field produced by the defective part fed with RF probing current, giving the name to Space Domain Reflectometry (SDR). SDR is a non-contact and nondestructive technique to localize open defects in package substrates, interconnections and semiconductor devices. It provides 2D failure isolation capability with defect localization resolution down to 50 microns. It is also capable of scanning long traces in Si. This paper describes the principles of the SDR and its application for the localization of open and high resistance defects. It then discusses some analysis methods for application optimization, and gives examples of test samples as well as case studies from actual failures.

scholarly journals Identifying the Optimal Subsets of Test Items through Adaptive Test for Cost Reduction of ICs

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 680
Author(s):  
Huaguo Liang ◽  
Jinlei Wan ◽  
Tai Song ◽  
Wangchao Hou
Keyword(s):  
Integrated Circuits ◽  
Cost Reduction ◽  
Bayesian Model ◽  
Test Methods ◽  
Test Time ◽  
Test Quality ◽  
Test Cost ◽  
Test Items ◽  
Adaptive Test ◽  
Test Escapes

With the growing complexity of integrated circuits (ICs), more and more test items are required in testing. However, the large number of invalid items (which narrowly pass the test) continues to increase the test time and, consequently, test costs. Aiming to address the problems of long test time and reduced test item efficiency, this paper presents a method which combines a fast correlation-based filter (FCBF) and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions. Experimental results demonstrate that the proposed method reduces test time by around 2.59% and leads to fewer test escapes compared with the recently adopted test methods. The study shows that the proposed method can effectively reduce the test cost without jeopardizing test quality excessively.

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

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