Variable measurement interval for channel-adaptive random access

Abstract This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.

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Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0077 ◽

2000 ◽

Author(s):

Srikanth Perungulam ◽

Scott Wills ◽

Greg Mekras

Keyword(s):

Cross Sections ◽

Digital Signal Processor ◽

Focused Ion Beam ◽

Ion Beam ◽

Random Access ◽

Digital Signal ◽

Yield Enhancement ◽

Final Conclusion ◽

Stage Separation ◽

Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

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Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1998p0373 ◽

1998 ◽

Author(s):

Phil Schani ◽

S. Subramanian ◽

Vince Soorholtz ◽

Pat Liston ◽

Jamey Moss ◽

...

Keyword(s):

Electron Microscopy ◽

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Temperature Sensitive ◽

Wafer Level ◽

Top Down ◽

Access Memory ◽

Transmission Electron ◽

Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0383 ◽

2012 ◽

Author(s):

Ramachandra Chitakudige ◽

Sarat Kumar Dash ◽

A.M. Khan

Keyword(s):

High Selectivity ◽

Electron Cyclotron Resonance ◽

Random Access ◽

Random Access Memory ◽

Access Memory ◽

Plasma System ◽

Poly Silicon ◽

Hazardous Gases ◽

Wet Etch ◽

Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

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Challenges and Benefits of Product-Like SRAM in Technology Development

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0362 ◽

2011 ◽

Author(s):

Felix Beaudoin ◽

Stephen Lucarini ◽

Fred Towler ◽

Stephen Wu ◽

Zhigang Song ◽

...

Keyword(s):

Technology Development ◽

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Development Phase ◽

High Complexity ◽

Access Memory ◽

Integration Schemes ◽

Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

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Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0128 ◽

2008 ◽

Author(s):

Steven B. Herschbein ◽

Hyoung H. Kang ◽

Scott L. Jansen ◽

Andrew S. Dalton

Keyword(s):

Flip Chip ◽

Focused Ion Beam ◽

Ion Beam ◽

Random Access ◽

Cell Counting ◽

Test Results ◽

Laboratory Procedure ◽

Memory Array ◽

Dual Beam ◽

Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

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