Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

2002 ◽  
Vol 124 (3) ◽  
pp. 234-239 ◽  
Author(s):  
Y. T. Lin ◽  
C. T. Peng ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Reliability Characteristics ◽  
Interconnect Technology

The demands for electronic packages with lower profile, lighter weight, and higher input/output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent demand high I/O density and good reliability characteristics have led to the evolution of ultra high-density non-solder interconnection, such as wire interconnect technology (WIT). New technology, which uses copper posts to replace the solder bumps as interconnections, has improved reliability. Moreover, this type of wafer level package produces higher I/O density, as well as ultra fine pitch. This research focuses on the reliability analysis, material selection and structural design of WIT packaging. This research employs finite element method (FEM) to analyze the physical behavior of packaging structures under thermal cycling conditions to compare the reliability characteristics of conventional wafer level and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature-dependent material properties will be applied to all models.

scholarly journals Wafer Level Packaging Technology Applied to Pixel Detectors

2021 ◽  
Vol 9 ◽  
Author(s):  
Paolo Conci ◽  
Giovanni Darbo ◽  
Andrea Gaudiello ◽  
Claudia Gemme ◽  
Stefano Girardi ◽  
...  
Keyword(s):  
High Energy Physics ◽  
High Energy ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Technical Requirements ◽  
Pixel Detectors ◽  
Single Sensor ◽  
Wafer Processing ◽  
Wafer Level Package ◽  
Energy Physics

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

BCB-Based Dry Film low k Permanent Polymer with sub 4-μm Vias for Advanced WLP and FO-WLP Applications

2015 ◽  
Vol 2015 (1) ◽  
pp. 000079-000085 ◽  
Author(s):  
Michael Toepper ◽  
Tanja Braun ◽  
Robert Gernhardt ◽  
Martin Wilke ◽  
Piotr Mackowiak ◽  
...  
Keyword(s):  
Laser Scanning ◽  
New Technology ◽  
Side Wall ◽  
Wafer Level ◽  
Major Barrier ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Low K ◽  
Metallization Process ◽  
Dry Film

There is a strong demand to increase the routing density of the RDL to match the requirements for future microelectronic systems which are mainly miniaturization and performance. Photo-resists for structuring the metallization or acting as a mold for electroplating are common for very fine lines and spaces due to the developments in the front-end processing. For example chemical amplified Photo-resists are now moving in the back-end and wafer level packaging process. The results are mainly governed by the performance of the equipment i.e. the photo-tool. This is different for the permanent dielectric polymer material. The major difference in photo-resists and dielectric photo-polymer are the different functions of the material systems. Photo-resists are only temporary masks for subsequent process steps like etching and plating. This is different for the photo-polymers which are a permanent part of the future systems. In this paper a new technology is discussed which uses a laser scanning ablation process and BCB-Based Dry Film low k Permanent Polymer. Laser ablation of polymers is in principle not a new technology. Low speed and high cost was the major barrier. But the combination of a scanning technology together with quartz masks has opened this technology to overcome the limitation of the current photo-polymer process. The new technology is described in detail and the results of structuring BCB-Based Films down to less than 4 μm via diameter in a 15 μm thick film has been shown. The via side wall can be controlled by the fluence of the laser pulse. Test structures have been designed and fabricated to demonstrate the excellent electrical resistivity of the vias using a two-layer metallization process.

On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou
Keyword(s):  
Technological Change ◽  
Flip Chip ◽  
Emerging Technologies ◽  
Unit Area ◽  
Form Factors ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Wafer Level Packaging ◽  
Area Array

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..

Solder fatigue of Wafer Level package assemblies. Comparison with flip chip BGA’S

2008 ◽  
Author(s):  
Charles Regard ◽  
Christian Gautier ◽  
Helene Fremont ◽  
Alexandre Val ◽  
Frederic Roullier ◽  
...  
Keyword(s):  
Flip Chip ◽  
Wafer Level ◽  
Solder Fatigue ◽  
Wafer Level Package

M-Series with Adaptive Patterning for High-Yield Fan-Out SIP

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000751-000773
Author(s):  
Craig Bishop ◽  
Suresh Jayaraman ◽  
Boyd Rogers ◽  
Chris Scanlan ◽  
Tim Olson
Keyword(s):  
New Technology ◽  
Minimum Size ◽  
High Yield ◽  
Wafer Level ◽  
Design Rules ◽  
Optical Scanner ◽  
Wafer Level Packaging ◽  
And Performance ◽  
The Cost ◽  
Semiconductor Chips

Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.

Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

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