Prospects for automotive SiP modules applying IC assembly and packaging technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000006-000012
Author(s):  
Tomohiro Furukawa ◽  
Takahiro Kasuga ◽  
Masato Umehara ◽  
Yuka Tamadate
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Interface Material ◽  
Heat Sources ◽  
Heat Spreader ◽  
Thermal Interface ◽  
Passive Components ◽  
Reflow Temperature ◽  
Assembly Technology

Abstract We develop a package that ensures quality complying with AEC-Q 100 Grade 2 which is in-vehicle quality from various flip chip mounting methods and bump sealing technology with underfill resin and mold resin. FC CSP with heat spreader mounted on the product which has started mass production since last year is in the lineup, The heat dissipation can be improved by attaching the heat spreader directly to the chip backside which are heat sources and the Thermal Interface Material (TIM), using our assembly technology of flip chip mounting and molding the periphery while exposing the chip backside. By adjusting the Coefficient of Thermal Expansion (CTE) and thickness of the material, we realize low warpage and low coplanarity at reflow temperature and product use temperature environment and reduce package displacement behavior, we will improve the secondary mountability to the motherboard and provide reliable packages. Furthermore, it can be applied to SiP modules. It is also possible to construct multiple chip modules by mounting multiple ICs or placing low-passive components around them. We will consider heat spreader mounting on multiple ICs that generate heat, and metal coating on the entire SiP module to have a structure that achieves both heat dissipation and electromagnetic shielding as a future idea.

Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

Precise, high throughput dispensing of thermal interface material in BGA packaging applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001391-001412
Author(s):  
Hanzhuang Liang ◽  
Linh Rolland
Keyword(s):  
High Throughput ◽  
Flip Chip ◽  
Consumer Electronics ◽  
Thermal Interface Material ◽  
Production Lines ◽  
Heat Spreader ◽  
Heavy Load ◽  
Thermal Interface ◽  
Wide Range ◽  
Complicated Geometries

In a flip chip BGA package, thermal interface materials (TIMs) are applied for thermal management between the die and the heat spreader or between the heat spreader and the heat sink to conduct the heat generated in the die during component operation. Without a thermal interface, the die will overheat and the components will not function properly. Advanced microelectronics packaging demands high and dynamic standards of its supplier industries in relation to speed, precision and flexibility. For example, the demands on functionality, power density and performance of the components within a die are largely enhanced along with TIM requirements for higher heat resistance. Manufacturers are being asked to apply TIMs on more dies in more complicated geometries and to dispense them during any packaging process. This brings increased challenges for TIM dispensing equipment, such as the ability to handle abrasive and dry TIMs at a high throughput while maintaining precision and repeatability. A high-precision, high-throughput TIM dispensing process has been developed to fill the gap between the traditional slower dispensing of simple patterns and the challenges from emerging package designs. This process is being used in flip chip BGA production lines in package applications from consumer electronics to automotive products. These production lines are in full 24/7 operation with each dispensing system running at 240 units per hour (uph) for audio-video consumer electronics, 360 uph for CPUs/GPUs on smart phones and 750 uph for automobile control panels and computation servers. In this new dispensing system, the valve can be tightly controlled to achieve high dispensing accuracy at fast speeds. The dispense pattern and route can be modified at no cost, in minutes, and during any step in the design or the assembly stage. Shapes that can be dispensed include dots, lines, boxes and circles with fine height and edge definitions of 25micron and 45micron. The process can cover a wide range of pattern dimensions between 0.5mm and 100mm at flow rates of 30–370 mg/sec at a repeatability of 3–15% three sigma. Even TIM that has viscosity as high as 1500kcPs with a heavy load of large and coarse particles such as metals, ceramic and glass beads can be dispensed using this equipment and process. New equipment and processes are under development to further push the limit on higher throughput and precision, increased flexibility and material dispensability.

Silicone Gel Thermal Interface Materials for High Heat Dissipation and Thermo-Mechanical Stress Management for Good Reliability Performance

2005 ◽  
Author(s):  
J. C. Matayabas ◽  
Vassou LeBonheur
Keyword(s):  
High Performance ◽  
Heat Dissipation ◽  
High Heat ◽  
Thermal Interface Material ◽  
Market Demand ◽  
Heat Spreader ◽  
Good Reliability ◽  
Theoretical Understanding ◽  
Thermal Interface ◽  
Silicone Gel

The recent trend in microprocessor architecture has been to increase the number of transistors (higher power), shrink processor size (smaller die), and increase clock speeds (higher frequency) in order to meet the market demand for high performance microprocessors. These have resulted in the escalation of power dissipation as well as the heat flux at the silicon die level. The Intel packaging technology development group has been challenged to develop packaging solutions that not only meet the package thermal targets but also the reliability requirements. As a result, an integrated heat spreading (IHS) package was developed, comprising a Cu based heat spreader and a first level thermal interface material (TIM) between the die and the heat spreader. Due to CTE mismatches between its different elements, the IHS package is subjected to high level of thermo-mechanical stresses which lead to severe failures post reliability testing. A significant amount of theoretical understanding of thermal resistance has been developed and applied to the development of TIM formulations, and it was found that the thermo-mechanical properties of the TIM material need to be optimized to mitigate the package reliability stresses. Several material and process solutions have been investigated using fundamental approaches, and, as a result of these efforts, low stress silicone gel TIM’s were developed. This paper provides an overview of the silicone gel TIM technologies investigated at Intel, and the key learnings from the fundamental material and package integration studies.

Thermal Interface Material Technology Advancements and Challenges: An Overview

2005 ◽  
Author(s):  
Ashay Dani ◽  
James C. Matayabas ◽  
Paul Koning
Keyword(s):  
Flip Chip ◽  
Phase Change Materials ◽  
Heat Dissipation ◽  
Low Cost ◽  
Thermal Interface Material ◽  
Next Generation ◽  
Material Technology ◽  
Thermal Interface ◽  
Flip Chip Packaging ◽  
Architecture And Design

With an increase in the number of transistors (higher power), shrinking processor size (smaller die), and increasing clock speeds (higher frequency) for next generation microprocessors, heat dissipation at the silicon die level has become a critical focus area for microprocessor architecture and design. In addition, power removal at low cost continues to remain the key challenge as we develop the next generation packaging technologies. Novel Thermal Interface Materials (TIM) are required to be designed and developed to meet these new package thermal targets. This paper presents an overview of the novel TIM technologies developed at Intel including greases, phase change materials (PCM), gels, polymer solder hybrids, and solder TIM for multiple generations of desktop, server and mobile microprocessors. The advantages and limitations of these TIM technologies in the thermal management of flip chip packaging are reviewed for Intel’s microprocessors.

Using In situ Capacitance Measurements to Monitor the Stability of Thermal Interface Materials in Complex PCB Assemblies

2010 ◽  
Vol 2010 (1) ◽  
pp. 000450-000457
Author(s):  
Michael Gaynes ◽  
Timothy Chainer ◽  
Edward Yarmchuk ◽  
John Torok ◽  
David Edwards ◽  
...  
Keyword(s):  
Thermal Cycle ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Circuit Board ◽  
Large Area ◽  
Voltage Transformer ◽  
Heat Spreader ◽  
Thermal Interface ◽  
Thermal Solution

A thermal solution for an array of voltage transformer modules which are cooled by a large area, common aluminum heat spreader for a high end server was evaluated using an in situ, capacitive bond line thermal measurement technique. The method measures the capacitance of a non-electrically conducting thermal interface material (TIM) between the electronic module and heat spreader to quantify the TIM bond line effective thickness during assembly and operation. The thermal resistance of the TIM has the same geometric dependence as the inverse of capacitance, therefore, the capacitive technique also provided a monitor of the thermal performance of the interface. This technique was applied to measure the bond line in real time during the assembly of the heat spreader to an array of 37 modules mounted on a printed circuit board. The results showed that the target bond lines were not achieved by application of a constant force alone on the heat spreader, and guided an improved assembly process. The mechanical motion of the TIM was monitored in situ during thermal cycling and found to fluctuate systematically from the hot to cold portions of the thermal cycle, either compressing or stretching the TIM respectively. The capacitive bond line trend showed thermal interface degradation vs. cycle count for several modules which was confirmed by disassembly and visual inspection. Areas of depleted TIM ranged as high as 25% of the module area. Several design and material changes were shown to improve the TIM stability. Power cycling tests were run in parallel to the thermal cycle tests to help relate the results to field performance. The capacitance technique enabled the development and verification of a thermal solution for a complex mechanical system early in the development cycle.

Thermal Resistance Analysis of Sn-Bi Solder Paste Used as Thermal Interface Material for Power Electronics Applications

2014 ◽  
Vol 136 (1) ◽  
Author(s):  
Rui Zhang ◽  
Jian Cai ◽  
Qian Wang ◽  
Jingwei Li ◽  
Yang Hu ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Power Electronics ◽  
Heat Dissipation ◽  
Laser Flash ◽  
Acoustic Microscopy ◽  
Thermal Interface Material ◽  
Solder Paste ◽  
Good Reliability ◽  
Thermal Interface ◽  
Power Modules

To promote heat dissipation in power electronics, we investigated the thermal conduction performance of Sn-Bi solder paste between two Cu plates. We measured the thermal resistance of Sn-Bi solder paste used as thermal interface material (TIM) by laser flash technique, and a thermal resistance less than 5 mm2 K/W was achieved for the Sn-Bi TIM. The Sn-Bi solder also showed a good reliability in terms of thermal resistance after thermal cycling, indicating that it can be a promising candidate for the TIM used for power electronics applications. In addition, we estimated the contact thermal resistance at the interface between the Sn-Bi solder and the Cu plate with the assistance of scanning acoustic microscopy. The experimental data showed that Sn-Bi solder paste could be a promising adhesive material used to attach power modules especially with a large size on the heat sink.

Thermal Analysis for Three-Dimensional Heat Spreader Integrated With Heat Sink

2003 ◽  
Author(s):  
Y. C. Wu ◽  
H. T. Chen ◽  
C. C. Lin ◽  
Y. H. Hung
Keyword(s):  
Heat Sink ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Sinks ◽  
Heat Sources ◽  
Heat Spreader ◽  
Discrete Heat Sources ◽  
Thermal Analyzer ◽  
Parametric Studies ◽  
Overall Resistance

An effective thermal analyzer for exploring the thermal performance of 3-D heat spreader having discrete heat sources integrated with heat sink has been successfully developed in the study. The thermal performances such as local temperature distributions and isotherms on heat spreader surfaces; and overall resistance of heat spreader/sink assembly are investigated. Besides, a series of parametric studies have been performed. The parameters and conditions explored include the size and heat dissipation rate of heat sources, size and material of heat spreaders and heat sinks, type of convection in heat sink, and contact conditions between heat spreader and heat sink. The superiority of the developed thermal analyzer through two sample cases having multi-discrete heat sources has finally been demonstrated.

Thin Film Multichip Packaging for High Temperature Digital Electronics

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000039-000045 ◽  
Author(s):  
Kun Fang ◽  
Rui Zhang ◽  
Tami Isaacs-Smith ◽  
R. Wayne Johnson ◽  
Emad Andarawis ◽  
...  
Keyword(s):  
Thin Film ◽  
High Temperature ◽  
Integrated Circuits ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Characteristics ◽  
Passive Components ◽  
Interlayer Dielectric ◽  
Base Ceramic ◽  
Film Substrate

Digital silicon carbide integrated circuits provide enhanced functionality for electronics in geothermal, aircraft and other high temperature applications. A multilayer thin film substrate technology has been developed to interconnect multiple SiC devices along with passive components. The conductor is vacuum deposited Ti/Ti:W/Au followed by an electroplated Au. A PECVD silicon nitride is used for the interlayer dielectric. Adhesion testing of the conductor and the dielectric was performed as deposited and after aging at 320°C. The electrical characteristics of the dielectric as a function of temperature were measured. Thermocompression flip chip bonding of Au stud bumped SiC die was used for electrical connection of the digital die to the thin film substrate metallization. Since polymer underfills are not compatible with 300°C operation, AlN was used as the base ceramic substrate to minimize the coefficient of thermal expansion mismatch between the SiC die and the substrate. Initial die shear results are presented.

Finite element analysis of lidded flip-chip packages: A study on the impact of thermal interface material compressibility and stress-free conditions on modeling predictions

2015 ◽  
Vol 2015 (1) ◽  
pp. 000151-000156
Author(s):  
Tuhin Sinha
Keyword(s):  
Flip Chip ◽  
Image Correlation ◽  
Thermal Interface Material ◽  
Element Analysis ◽  
Thermal Interface ◽  
Strong Function ◽  
Linear Elastic ◽  
Fea Modeling ◽  
Predicted Values ◽  
The Impact

In this paper, we present the effects of assumptions made about the constitutive behavior of a cured, silicone gel type thermal interface material (TIM) and the package stress-free conditions on FEA modeling predictions. The focus will be on the deformations (or warpage) predicted by the models for lidded flip-chip packages. It is critical for such warpage predictions to be close to experimental measurements for accurate projection of mechanical stresses and strains in a package. Digital Image Correlation (DIC) warpage measurements on flip-chip modules are compared against the predicted values and the impact of above-mentioned assumptions will be discussed. It will be shown that the TIM mechanical and thereby, thermal degradation is a strong function of the TIM compressibility and stress-free condition assumptions. Bounds of non-linear elastic modeling technique for the TIM and guidelines for conducting numerical analysis for lidded flip-chip packages will be provided.

A review of thermal interface material fabrication method toward enhancing heat dissipation

2020 ◽  
Author(s):  
Raihana Bahru ◽  
Mohd Faiz Muaz Ahmad Zamri ◽  
Abd Halim Shamsuddin ◽  
Norazuwana Shaari ◽  
Mohd Ambri Mohamed
Keyword(s):  
Heat Dissipation ◽  
Thermal Interface Material ◽  
Fabrication Method ◽  
Thermal Interface ◽  
Material Fabrication
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