Development of Process for Wafer Scale Encapsulation of Devices With Very Wide Trenches

Author(s):  
Vipin Ayanoor-Vitikkate ◽  
Kuan-Lin Chen ◽  
Kuan-Tae Park ◽  
Thomas W. Kenny

A Wafer scale encapsulation process has been developed for devices that require wide gaps. In this experiment, we focus on devices that have gaps or trenches 10-20μm wide. This process can also be applied to larger gaps of the order of 50-100μm. The chief focus of the process development is to achieve a wafer scale encapsulation technique, which can avoid deposition of very thick LPVCD oxide. Once the processing and encapsulation is carried out, SEM images are taken to ensure that the device is completely released and no sacrificial material is left behind.

2005 ◽  
Author(s):  
Hongjun Zeng ◽  
Alan Feinerman ◽  
Zhiliang Wan

A metal sacrificial method has been investigated for creation of microchannels by galvanic corrosion in a metal multilayer. To achieve the fastest sacrificial metal combination, different metals and the corresponding etchants are chosen. Channels from 50 μm to 1 μm wide, 0.2 μm high, and 1500 μm long, as well as the channel array is fabricated, using Cr/Cu galvanic metal couple as sacrificial material. The relationship between the etching front vs. the etching time, and the relationship of the etch rate vs. channel width is measured and compared with the etching performance of the single metal. The measurement shows there is approximately 10 times faster etching in the galvanic coupled metals than that in the single metal. SEM images of the channels and channel array made by this method are presented. This method is compatible with the conventional VLSI process, and has the potential for fabricating microchannels with submicron or even nanometer cross section.


2015 ◽  
Vol 24 (6) ◽  
pp. 1687-1694 ◽  
Author(s):  
Chae Hyuck Ahn ◽  
Eldwin J. Ng ◽  
Vu A. Hong ◽  
Julia Huynh ◽  
Shasha Wang ◽  
...  

2020 ◽  
Vol 20 (4) ◽  
pp. 929 ◽  
Author(s):  
Agnes Dyah Novitasari Lestari ◽  
Dwi Siswanta ◽  
Ronny Martien ◽  
Mudasir Mudasir

This study aims to investigate the synthesis and characterization of β-carotene encapsulated in the blending matrices of starch (native and hydrolyzed starch)-chitosan/TPP (tripolyphosphate) by examining the effects of starch-to-chitosan weight ratio, β-carotene addition level, and TPP addition level on the encapsulation efficiency (EE) and loading capacity (LC); and to evaluate their storage stability. The encapsulation was done by the dropwise addition of ethanolic β-carotene dispersion into the blending matrices. The results of XRD analysis show that the encapsulation process significantly decreases the crystallinity of the starches, chitosan, and β-carotene. Scanning electron microscope (SEM) images reveal that the encapsulation products form irregular lumps. The EE and LC tend to increase with the increase in polymer fraction of matrices and β-carotene addition level, and with the decrease in TPP addition level. The addition of chitosan and the replacement of native starch by hydrolyzed starch tend to increase storage stability of β-carotene encapsulated in the starch matrix because chitosan can act as a good film-forming and antioxidant, while hydrolyzed starch contains amylose amylopectin with a short chain which is better in film-forming ability. These results promote the use of the hydrolyzed starch-chitosan/TPP as a matrix to enhance the stability β-carotene via encapsulations.


Author(s):  
Lou Hermans ◽  
Raffa Borzi

Within the CMORE program IMEC translates proven, Si technology based device concepts and process flows in industrially and commercially viable products and manufacturing flows. Si based IC processing technologies are, and will continue for a long time to be at the basis of many product innovations. Miniaturization and integration have proven to be powerful tools for the conception of novel products. These technologies are usually referred to a “Heterogeneous Integration” or “More Then Moore” in contrast to the pure CMOS scaling referred to as “More Moore”. Many of these new products combine high performance, multiple functions and compactness with consumer price levels. In other cases, miniaturization leads to unprecedented performances, resulting in products which were not feasible before. New device concepts are often generated at university, governmental or industrial laboratories. Although these environments are very well suited for proving technical feasibility, they are often less well equipped and organized for product development and the development of corresponding Si processing flow. On the other hand the prime focus of Si or MEMS foundries, be it merchant or captive, is wafer throughput, resulting in little interest for allocating processing capacity to product and process development, when product market acceptance still has to be proven and high volume production is still questionable. In addition development activities introduce risks on contamination and equipment failures leading to a reduction of the fab capacity. This gap between “proof-of-concept” and volume manufacturing offers new opportunities for R&D fabs traditionally active in CMOS scaling. These “development and prototyping” fabs have the infrastructure, processing know-how and procedures in place to efficiently translate device concepts into products and to develop industrially viable fabrication processes. In addition they have the flexibility and experience to introduce very quickly new materials and associated equipment, while keeping in mind compatibility with the industrial foundry environment, where final production will take place. Close cooperation with material and equipment suppliers is very important in that respect. In many projects executed at IMEC, wafer scale interconnects and/or wafer scale packaging are important aspects of the final device and therefore should be included from the start of the project. In this paper the IMEC approach and capabilities will be presented and illustrated with a number of past and ongoing projects.


2009 ◽  
Vol 156 (2) ◽  
pp. 275-283 ◽  
Author(s):  
Vipin Ayanoor-Vitikkate ◽  
Kuan-lin Chen ◽  
Woo-Tae Park ◽  
Thomas W. Kenny

Author(s):  
M. D. Coutts ◽  
E. R. Levin

On tilting samples in an SEM, the image contrast between two elements, x and y often decreases to zero at θε, which we call the no-contrast angle. At angles above θε the contrast is reversed, θ being the angle between the specimen normal and the incident beam. The available contrast between two elements, x and y, in the SEM can be defined as,(1)where ix and iy are the total number of reflected and secondary electrons, leaving x and y respectively. It can easily be shown that for the element x,(2)where ib is the beam current, isp the specimen absorbed current, δo the secondary emission at normal incidence, k is a constant, and m the reflected electron coefficient.


Author(s):  
P. B. Basham ◽  
H. L. Tsai

The use of transmission electron microscopy (TEM) to support process development of advanced microelectronic devices is often challenged by a large amount of samples submitted from wafer fabrication areas and specific-spot analysis. Improving the TEM sample preparation techniques for a fast turnaround time is critical in order to provide a timely support for customers and improve the utilization of TEM. For the specific-area sample preparation, a technique which can be easily prepared with the least amount of effort is preferred. For these reasons, we have developed several techniques which have greatly facilitated the TEM sample preparation.For specific-area analysis, the use of a copper grid with a small hole is found to be very useful. With this small-hole grid technique, TEM sample preparation can be proceeded by well-established conventional methods. The sample is first polished to the area of interest, which is then carefully positioned inside the hole. This polished side is placed against the grid by epoxy Fig. 1 is an optical image of a TEM cross-section after dimpling to light transmission.


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