Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.

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Development of an Analytical Model to a Temperature Distribution of First Level Package With a Non-Uniformly Powered Die

Volume 5: Electronics and Photonics ◽

10.1115/imece2007-43736 ◽

2007 ◽

Cited By ~ 1

Author(s):

Abhijit Kaisare ◽

Dereje Agonafer ◽

A. Haji-Sheikh ◽

Greg Chrysler ◽

Ravi Mahajan

Keyword(s):

Heat Flux ◽

Temperature Distribution ◽

Analytical Model ◽

Functional Integration ◽

Thermal Design ◽

Junction Temperature ◽

Direct Result ◽

Uniform Heat Flux ◽

Chip Surface ◽

Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work has been done which includes numerical analysis and thermal Based optimization of a typical package consisting of a non-uniformly powered die, heat spreader, TIM I &II and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a non-uniformly powered die is carried out for the first time. The analytical model for two layer bodies developed by Haji-Sheikh et al. is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology will be applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution will be carried out using developed numerical model.

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Development of Analytical Model to a Temperature Distribution of a First Level Package With a Nonuniformly Powered Die

Journal of Electronic Packaging ◽

10.1115/1.3068303 ◽

2009 ◽

Vol 131 (1) ◽

Cited By ~ 2

Author(s):

Abhijit Kaisare ◽

Dereje Agonafer ◽

A. Haji-Sheikh ◽

Greg Chrysler ◽

Ravi Mahajan

Keyword(s):

Heat Flux ◽

Temperature Distribution ◽

San Francisco ◽

Analytical Model ◽

Functional Integration ◽

Thermal Design ◽

Junction Temperature ◽

Direct Result ◽

Functional Block ◽

Functional Components

Microprocessors continue to grow in capabilities, complexity, and performance. Microprocessors typically integrate functional components such as logic and level two cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly nonuniform, and the assumption of a uniform heat flux across the die surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work (Kaisare et al., 2005, “Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die,” InterPACK 2005, San Francisco, CA, Jul. 17–22) has been done, which includes numerical analysis and thermal based optimization of a typical package consisting of a nonuniformly powered die, heat spreader, thermal interface materials I and II, and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a nonuniformly powered die is carried out for the first time. The analytical model for two-layer bodies developed by Haji-Sheikh et al. (2003, “Steady-State Heat Conduction in Multi-Layer Bodies,” Int. J. Heat Mass Transfer, 46(13), pp. 2363–2379) is extended to this typical package, which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology is applied to solve the equations for various surfaces to calculate the maximum junction temperature for a given multilayer body. Finally validation of the analytical solution is carried out using previously developed numerical model.

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Approximate Analytical Model for a First Level Package With Non-Uniformly Powered Die

Heat Transfer, Volume 3 ◽

10.1115/imece2006-13436 ◽

2006 ◽

Cited By ~ 1

Author(s):

Abhijit Kaisare ◽

Dereje Agonafer ◽

A. Haji-Sheikh ◽

Greg Chrysler ◽

Ravi Mahajan

Keyword(s):

Thermal Resistance ◽

Analytical Model ◽

Functional Integration ◽

Thermal Design ◽

Junction Temperature ◽

Direct Result ◽

Design Guideline ◽

Functional Blocks ◽

Distribution Of Power ◽

Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.

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Development of a Numerical Model for Non-Uniformly Powered Die to Improve Both Thermal and Device Clock Performance

ASME 2009 InterPACK Conference, Volume 2 ◽

10.1115/interpack2009-89188 ◽

2009 ◽

Cited By ~ 5

Author(s):

Saket Karajgikar ◽

Dereje Agonafer ◽

Kanad Ghose ◽

Bahgat Sammakia ◽

Cristina Amon ◽

...

Keyword(s):

Power Distribution ◽

High Speed ◽

Junction Temperature ◽

Total Power ◽

Maximum Temperature ◽

Large Temperature ◽

Computer Performance ◽

Performance Loss ◽

Functional Blocks ◽

Functional Components

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional blocks dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effect on computer performance and product reliability as well as yield. Moving the functional blocks may reduce the junction temperature but can also affect the performance by a factor as high as 35%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 82.4°C and 94.5°C with a corresponding penalty on the performance of 35% and 0% respectively. The optimized location of the functional blocks resulted in a temperature of 83.2°C for a performance loss of 5%.

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Spray Cooling for Time Resolved Emission Measurements of ICs

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0018 ◽

2004 ◽

Author(s):

Rama R. Goruganthu ◽

David Bethke ◽

Shawn McBride ◽

Tom Crawford ◽

Jonathan Frank ◽

...

Keyword(s):

Heat Flux ◽

Thermal Performance ◽

Flip Chip ◽

Cooling System ◽

Spray Cooling ◽

Junction Temperature ◽

Maximum Temperature ◽

Uniform Heat Flux ◽

High Heat Flux ◽

Time Resolved

Abstract Spray cooling is implemented on an engineering tool for Time Resolved Emission measurements using a silicon solid immersion lens to achieve high spatial resolution and for probing high heat flux devices. Thermal performance is characterized using a thermal test vehicle consisting of a 4x3 array of cells each with a heater element and a thermal diode to monitor the temperature within the cell. The flip-chip packaged TTV is operated to achieve uniform heat flux across the die. The temperature distribution across the die is measured on the 4x3 grid of the die for various heat loads up to 180 W with corresponding heat flux of 204 W/cm2. Using water as coolant the maximum temperature differential across the die was about 30 °C while keeping the maximum junction temperature below 95 °C and at a heat flux of 200 W/cm2. Details of the thermal performance of spray cooling system as a function of flow rate, coolant

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Thermal Design of a Satellite Borne FPGA

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.52-54.1411 ◽

2011 ◽

Vol 52-54 ◽

pp. 1411-1414 ◽

Cited By ~ 1

Author(s):

Bo Chen

Keyword(s):

Finite Element Analysis ◽

Finite Element ◽

Heat Sink ◽

Thermal Design ◽

Junction Temperature ◽

Element Analysis

Thermal design and analysis of a satellite borne FPGA is described in this paper. Thermal-conductive glue, vias and an aluminum bar were used to the FPGA and the PCB under the FPGA in order to help conduct the heat of the FPGA to heat sink. The results of finite element analysis showed that the case temperature of the FPGA decreased from 132.5°C to 55.4°C and the junction temperature decreased from 136.1°C to59.0 °C after the thermal design, which matches the requirements of thermal design.

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Microstructured Surfaces for Enhanced Pool Boiling Heat Transfer

Volume 10: Heat and Mass Transport Processes, Parts A and B ◽

10.1115/imece2011-65169 ◽

2011 ◽

Cited By ~ 1

Author(s):

Kuang-Han Chu ◽

Ryan Enright ◽

Evelyn N. Wang

Keyword(s):

Heat Transfer ◽

Heat Flux ◽

Boiling Heat Transfer ◽

Pool Boiling ◽

Heat Removal ◽

Design Guidelines ◽

Complete Wetting ◽

Structured Surfaces ◽

Microstructured Surfaces ◽

Wide Range

We experimentally investigated pool boiling on microstructured surfaces which demonstrate high critical heat flux (CHF) by enhancing wettability. The microstructures were designed to provide a wide range of well-defined surface roughness to study roughness-augmented wettability on CHF. A maximum CHF of 196 W/cm2 and heat transfer coefficient (h) greater than 80 kW/m2K were achieved. To explain the experimental results, a model extended from a correlation developed by Kandlikar was developed, which well predicts CHF in the complete wetting regime where the apparent liquid contact angle is zero. The model offers a first step towards understanding complex pool boiling processes and developing models to accurately predict CHF on structured surfaces. The insights gained from this work provide design guidelines for new surface technologies with higher heat removal capability that can be effectively used by industry.

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Thermal design of infrared detector components in complex heat flux

Infrared and Laser Engineering ◽

10.3788/irla201645.0904002 ◽

2016 ◽

Vol 45 (9) ◽

pp. 0904002 ◽

Cited By ~ 1

Author(s):

李强 Li Qiang ◽

陈立恒 Chen Liheng

Keyword(s):

Heat Flux ◽

Infrared Detector ◽

Thermal Design

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An Investigation Into the Potential of Low-Reynolds Number Eddy Viscosity Turbulent Flow Models to Predict Electronic Component Operational Temperature

Journal of Electronic Packaging ◽

10.1115/1.1849234 ◽

2005 ◽

Vol 127 (1) ◽

pp. 67-75 ◽

Cited By ~ 6

Author(s):

Peter Rodgers ◽

Vale´rie Eveloy ◽

M. S. J. Hashmi

Keyword(s):

Thermal Analysis ◽

Reynolds Number ◽

Eddy Viscosity ◽

Predictive Accuracy ◽

Low Reynolds Number ◽

Turbulence Models ◽

Thermal Design ◽

Junction Temperature ◽

Temperature Prediction ◽

Low Reynolds

The flow modeling approaches employed in computational fluid dynamics (CFD) codes dedicated to the thermal analysis of electronic equipment are generally not specific for the analysis of forced airflows over populated electronic boards. This limitation has been previously highlighted (Eveloy, V. et al., 2004, IEEE Trans. Compon., Packag., Technol. 27, pp. 268–282), with component junction temperature prediction errors of up to 35% reported. This study evaluates the potential of three candidate low-Reynolds number eddy viscosity turbulence models to improve predictive accuracy. An array of fifteen board-mounted PQFPs is analyzed in a 4 m/s airflow. Using the shear stress transport k-ω model, significant improvements in component junction temperature prediction accuracy are obtained relative to the standard high-Reynolds number k-ε model, which are attributed to better prediction of both board leading edge heat transfer and component thermal interaction. Such improvements would enable parametric analysis of product thermal performance to be undertaken with greater confidence in the thermal design process, and the generation of more accurate temperature boundary conditions for use in Physics-of-Failure based reliability prediction methods. The case is made for vendors of CFD codes dedicated to the thermal analysis of electronics to consider the adoption of eddy viscosity turbulence models more suited to board-level analysis.

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