Development of a Numerical Model for Non-Uniformly Powered Die to Improve Both Thermal and Device Clock Performance

2009 ◽  
Author(s):  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Kanad Ghose ◽  
Bahgat Sammakia ◽  
Cristina Amon ◽  
...  
Keyword(s):  
Power Distribution ◽  
High Speed ◽  
Junction Temperature ◽  
Total Power ◽  
Maximum Temperature ◽  
Large Temperature ◽  
Computer Performance ◽  
Performance Loss ◽  
Functional Blocks ◽  
Functional Components

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional blocks dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effect on computer performance and product reliability as well as yield. Moving the functional blocks may reduce the junction temperature but can also affect the performance by a factor as high as 35%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 82.4°C and 94.5°C with a corresponding penalty on the performance of 35% and 0% respectively. The optimized location of the functional blocks resulted in a temperature of 83.2°C for a performance loss of 5%.

Effect of Relocation of Functional Units of a Non-Uniformly Powered Microprocessor on Thermal and Device Clock Performance

2009 ◽  
Author(s):  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Kanad Ghose ◽  
Bahgat Sammakia ◽  
Cristina Amon ◽  
...  
Keyword(s):  
Power Distribution ◽  
High Speed ◽  
Junction Temperature ◽  
Total Power ◽  
Maximum Temperature ◽  
Large Temperature ◽  
Computer Performance ◽  
L2 Cache ◽  
Functional Units ◽  
Functional Components

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional units dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effects on computer performance, product reliability, and yield. Moving the functional units may reduce the junction temperature but can also affect performance by as much as 30%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 56.6°C and 62.2°C with a corresponding penalty on the performance of 14% and 0% respectively. The numerical analysis was performed for 90 nm Pentium® IV Northwood architecture at 3 GHz clock speed.

Multi-Objective Optimization to Improve Both Thermal and Device Performance of a Nonuniformly Powered Micro-Architecture

2010 ◽  
Vol 132 (2) ◽  
Author(s):  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Kanad Ghose ◽  
Bahgat Sammakia ◽  
Cristina Amon ◽  
...  
Keyword(s):  
Thermal Design ◽  
Junction Temperature ◽  
Total Power ◽  
Multi Objective Optimization ◽  
Computer Performance ◽  
Multi Objective ◽  
Performance Loss ◽  
Clock Speed ◽  
Functional Units ◽  
Design Power

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, and memory controller has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional units dissipate little or no power. This highly nonuniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effects on computer performance, product reliability, and yield. Moving the functional units may reduce the junction temperature but can affect performance by a factor as much as 30%. In this paper, a multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. The analysis was performed for 90 nm Pentium IV Northwood architecture operating at 3 GHz clock speed. Each functional unit on the die has a specific role, so functional units with similar roles were grouped together. Thus, the actual Pentium IV die was divided into four groups (front end, execution cores, bus and L2, and out-of-order engine). Repositioning constraints were determined using circuit delay models of major functional units in a micro-architectural simulator. Thus, depending on the scenario, relocating functional units can result in virtually no performance loss (less than 2% is assumed to be minimal and is reported as 0%) to as much as 30% performance loss. From the results, the minimum and the maximum temperatures were 56.6°C and 62.2°C. This ΔT corresponds to thermal design power of 60.2 W. For microprocessors with higher thermal design power (115 W) and operating at higher clock speed, higher ΔT can be realized. Based on this paper’s analysis, the optimized scenario resulted in a junction temperature of 56.6°C at the cost of a 14% performance loss.

Approximate Analytical Model for a First Level Package With Non-Uniformly Powered Die

2006 ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Thermal Resistance ◽  
Analytical Model ◽  
Functional Integration ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Design Guideline ◽  
Functional Blocks ◽  
Distribution Of Power ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.

Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die

2005 ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Heat Flux ◽  
Functional Integration ◽  
Design Guidelines ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Chip Surface ◽  
Functional Block ◽  
Functional Blocks ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.

Strip-and-Zone Micro-Channel Liquid Cooling of Integrated Circuits Chips With Non-Uniform Power Distributions

2013 ◽  
Author(s):  
Yu Zhang ◽  
Yubai Li ◽  
Xin Li ◽  
Shi-Chune Yao
Keyword(s):  
Integrated Circuit ◽  
Power Distribution ◽  
Channel Width ◽  
Total Power ◽  
Maximum Temperature ◽  
Air Cooling ◽  
Micro Channel ◽  
Liquid Cooling ◽  
Micro Channels ◽  
Parallel Strips

For a high-power integrated circuit (IC), it is desirable to cool with the liquid micro-channels. However, the non-uniform power distribution of the IC is a great challenge. In this paper, the strip-and-zone strategy is presented. First, the optimal channel-width assuming a uniform power distribution of the total chip power is considered as a nominal situation. Then, according to the distribution of the power density of the power blocks on chip, the micro-channels are divided into several parallel strips with various zones in these strips. A further optimization of the channel-width of each zone in the strips shall be made that a higher heat transfer coefficient will occur in the zones of higher heat flux, while the strips of higher total power will have same or less flow resistances. As a result, under the same pressure drop among all the strips, same or more flow will occur at the strips of higher total power and the maximum temperature on the chip is reduced. Illustration of this strip-and-zone micro-channel liquid cooling design is provided through a design case of an IC chip with realistic power distribution. Comparing with the same chip at the air cooling and at the micro-channel cooling with the nominal channel-width, the chip at strip-and-zone micro-channel liquid cooling yields the lowest surface temperature as expected.

scholarly journals Experimental Measurement of the Temperature Rise Generated During Dynamic Crack Growth in Metals

1990 ◽  
Vol 43 (5S) ◽  
pp. S260-S265 ◽  
Author(s):  
Alan T. Zehnder ◽  
Ares J. Rosakis
Keyword(s):  
Fracture Toughness ◽  
Dynamic Fracture ◽  
High Speed ◽  
Crack Tip ◽  
Dynamic Fracture Toughness ◽  
Plastic Work ◽  
Temperature Fields ◽  
Plastic Strain Rate ◽  
Maximum Temperature ◽  
Large Temperature

During the high speed propagation of cracks, large temperature increases occur at the crack tip due to the intense dissipation of plastic work there. This increased temperature may have a significant effect of the material’s dynamic fracture toughness. An experimental investigation of the temperature fields at the tip of dynamically propagating cracks in 4340 steel was performed using a focused array of high speed, infrared detectors. Temperature fields were measured for cracks growing at speeds from 700m/s to 1900m/s. Maximum temperature increases were as high as 465°C. The temperature fields were differentiated to determine the plastic work rate distribution at the crack tip and to estimate the plastic strain rate. Effects of crack tip heating on dynamic fracture toughness are discussed.

Spray Cooling for Time Resolved Emission Measurements of ICs

2004 ◽  
Author(s):  
Rama R. Goruganthu ◽  
David Bethke ◽  
Shawn McBride ◽  
Tom Crawford ◽  
Jonathan Frank ◽  
...  
Keyword(s):  
Heat Flux ◽  
Thermal Performance ◽  
Flip Chip ◽  
Cooling System ◽  
Spray Cooling ◽  
Junction Temperature ◽  
Maximum Temperature ◽  
Uniform Heat Flux ◽  
High Heat Flux ◽  
Time Resolved

Abstract Spray cooling is implemented on an engineering tool for Time Resolved Emission measurements using a silicon solid immersion lens to achieve high spatial resolution and for probing high heat flux devices. Thermal performance is characterized using a thermal test vehicle consisting of a 4x3 array of cells each with a heater element and a thermal diode to monitor the temperature within the cell. The flip-chip packaged TTV is operated to achieve uniform heat flux across the die. The temperature distribution across the die is measured on the 4x3 grid of the die for various heat loads up to 180 W with corresponding heat flux of 204 W/cm2. Using water as coolant the maximum temperature differential across the die was about 30 °C while keeping the maximum junction temperature below 95 °C and at a heat flux of 200 W/cm2. Details of the thermal performance of spray cooling system as a function of flow rate, coolant

Improving the efficiency of oilfield electric power distribution

2019 ◽  
pp. 79-87
Author(s):  
Yu. F. Yu. F. Romaniuk ◽  
О. V. Solomchak ◽  
М. V. Hlozhyk
Keyword(s):  
Power Distribution ◽  
Reactive Power ◽  
Power Transmission ◽  
Transmission Efficiency ◽  
Active Power ◽  
Oil Field ◽  
Total Power ◽  
Simultaneous Increase ◽  
Active Load ◽  
Step Down

The issues of increasing the efficiency of electricity transmission to consumers with different nature of their load are considered. The dependence of the efficiency of the electric network of the oil field, consisting of a power line and a step-down transformer, on the total load power at various ratios between the active and reactive components of the power is analyzed, and the conditions under which the maximum transmission efficiency can be ensured are determined. It is shown by examples that the power transmission efficiency depends not only on the active load, but also largely on its reactive load. In the presence of a constant reactive load and an increase in active load, the total power increases and the power transmission efficiency decreases. In the low-load mode, the schedule for changing the power transmission efficiency approaches a parabolic form, since the influence of the active load on the amount of active power loss decreases, and their value will mainly depend on reactive load, which remains unchanged. The efficiency reaches its maximum value provided that the active and reactive components of the power are equal. In the case of a different ratio between them, the efficiency decreases. With a simultaneous increase in active and reactive loads and a constant value of the power factor, the power transmission efficiency is significantly reduced due to an increase in losses. With a constant active load and an increase in reactive load, efficiency of power transmission decreases, since with an increase in reactive load, losses of active power increase, while the active power remains unchanged. The second condition, under which the line efficiency will be maximum, is full compensation of reactive power.  Therefore, in order to increase the efficiency of power transmission, it is necessary to compensate for the reactive load, which can reduce the loss of electricity and the cost of its payment and improve the quality of electricity. Other methods are also proposed to increase the efficiency of power transmission by regulating the voltage level in the power center, reducing the equivalent resistance of the line wires, optimizing the loading of the transformers of the step-down substations and ensuring the economic modes of their operation.

Maximum Temperature Through a Yttrium Stabilized Zirconia Ceramic After Er,Cr:YSGG Laser Irradiation

2020 ◽  
Vol 02 ◽  
Author(s):  
Laurel Stringer ◽  
Sarah Malley ◽  
Darrell M. Hutto ◽  
Jason A. Griggs ◽  
Susana M. Salazar Marocho
Keyword(s):  
High Speed ◽  
Potential Method ◽  
Maximum Temperature ◽  
Zirconia Ceramic ◽  
Tooth Pulp ◽  
Control Group ◽  
Stabilized Zirconia ◽  
Significant Difference ◽  
Power Setting ◽  
Group A

Background: The most common approach to remove yttria stabilized zirconia (YSZ) fixed-dental prostheses (FDPs) is by means of diamond burs attached to a high-speed handpiece. This process is time-consuming and destructive. The use of lasers over mechanical instrumentation for removal of FDPs can lead to efficient and predictable restoration retrievability. However, the heat produced might damage the tooth pulp (>42˚C). Objective: The purpose of this study was to determine the maximum temperature (T) reached during the use of different settings of the erbium, chromium:yttrium-scandium-gallium-garnet Er,Cr:YSGG laser through a YSZ ceramic. Methods: YSZ slices (1 mm thick) were assigned into 7 groups. For the control group, a diamond bur was used to cut a 1 mm groove into the YSZ slices. For the 6 experimental groups, the laser was operated at a constant combination of 33% water and 66% air during 30 s with two different power settings (W) at three frequencies (PPS), as follows (W/PPS): 2.5/20, 2.5/30, 2.5/45, 4.5/20, 4.5/30, 4.5/45. The T through the YSZ slice was recorded in degrees Celsius by using a digital thermometer with a K thermocouple. Results: The median T of the control group was 26.5˚C. The use of 4.5 W resulted in the median T (˚C) of 44.2 at 20 PPS, 53.3 at 30 PPS, and 58.9 at 45 PPS, while 2.5 W showed 34.6, 31.6, and 25.0 at 20, 30, and 45 PPS, respectively. KruskalWallis one-way ANOVA showed that within each power setting, the T was similar. The high power and lowest frequency (4.5/20) showed no significant difference from the 2.5 W settings and the control group. Conclusion: The lower power setting (2.5 W) is a potential method for the use of the Er,Cr:YSGG laser to debond YSZ structures. The higher power (4.5 W) with high frequencies (30 and 45 PPS) is unsuitable.

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