Chirped Superlattices as Adjustable Strain Platforms for Metamorphic Semiconductor Devices

Chirped superlattices are of interest as buffer layers in metamorphic semiconductor device structures, because they can combine the mismatch accommodating properties of compositionally-graded layers with the dislocation filtering properties of superlattices. Important practical aspects of the chirped superlattice as a buffer layer are the surface strain and surface in-plane lattice constant. In this work two basic types of InGaAs/GaAs chirped superlattice buffers have been studied. In design I (composition modulated), the average composition is varied by modulating the composition of one of the two layers in the superlattice period, but the individual layer thicknesses were fixed. In design II (thickness modulated), the individual layer thicknesses were modulated, but the compositions were fixed. In this paper the surface strain and surface in-plane lattice constant for these chirped superlattices are presented as functions of the top composition and period for each of these basic designs.

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Light Scattering Analysis of Strained-Layer Superlattices

MRS Proceedings ◽

10.1557/proc-103-265 ◽

1987 ◽

Vol 103 ◽

Author(s):

G. P. Schwartz ◽

G. J. Gualtieri ◽

W. A. Sunder

Keyword(s):

Light Scattering ◽

Raman Scattering ◽

Acoustic Phonon ◽

Individual Layer ◽

Strained Layer ◽

Phonon Spectra ◽

The Individual ◽

Strained Layer Superlattices ◽

Superlattice Period

ABSTRACTRaman scattering has been used to examine strained-layer GaSb/AlSb superlattices for a variety of growth imperfections. Analysis of zone-folded acoustic phonon spectra permit a determination of the superlattice period, the individual layer widths, some estimate of the interfacial widths, and evidence for variations in layer thicknesses.

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In-plane lattice constant tuning of an oxide substrate with Ba1−xSrxTiO3 and BaTiO3 buffer layers

Applied Physics Letters ◽

10.1063/1.1484242 ◽

2002 ◽

Vol 80 (23) ◽

pp. 4437-4439 ◽

Cited By ~ 32

Author(s):

K. Terai ◽

M. Lippmaa ◽

P. Ahmet ◽

T. Chikyow ◽

T. Fujii ◽

...

Keyword(s):

Lattice Constant ◽

Buffer Layers ◽

Plane Lattice ◽

Oxide Substrate

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The Use of Superlattices to Block the Propagation of Dislocations in Semiconductors

MRS Proceedings ◽

10.1557/proc-148-217 ◽

1989 ◽

Vol 148 ◽

Cited By ~ 10

Author(s):

A.E. Blakeslee

Keyword(s):

Layer Thickness ◽

Critical Thickness ◽

Semiconductor Device ◽

Growth Conditions ◽

Buffer Layers ◽

Effectiveness Factors ◽

Dislocation Densities ◽

Device Structures

ABSTRACTSince the discovery in 1973 that GaAs/GaAsP superlattices can be grown with low dislocation densities, considerable interest has developed in utilizing superlattices as dislocation filters in multilayer semiconductor device structures. Many attempts to implement this process have been described, with varying degrees of success being achieved. Some investigators have reported favorable results; some have observed no effect; and in some cases the situation was actually made worse. This paper analyzes these reports and attempts to clarify the confusion that has arisen. Suggestions are made for improved effectiveness. Factors considered include the strain between layers, the layer thickness, the concept of critical thickness, the dislocation geometry, and the influence of buffer layers and growth conditions.

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Behavior of contact-silicided TFSOI gate structures

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100172036 ◽

1994 ◽

Vol 52 ◽

pp. 860-861

Author(s):

N. David Theodore ◽

Juergen Foerstner ◽

Peter Fejes

Keyword(s):

Semiconductor Device ◽

Series Resistance ◽

Field Effect Transistors ◽

Silicon Layer ◽

Device Fabrication ◽

Silicon On Insulator ◽

Continuous Layer ◽

Buried Oxide ◽

Device Structures ◽

Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0305 ◽

2011 ◽

Author(s):

Liew Kaeng Nan ◽

Lee Meng Lung

Keyword(s):

Sample Preparation ◽

Semiconductor Device ◽

Ion Beam ◽

Critical Dimension ◽

Low Energy ◽

Ex Situ ◽

Good Image Quality ◽

Ion Beam Etching ◽

Device Structures ◽

Common Technique

Abstract Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.

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Polarization effects in nitride semiconductor device structures and performance of modulation doped field effect transistors

Solid-State Electronics ◽

10.1016/s0038-1101(99)00146-x ◽

1999 ◽

Vol 43 (10) ◽

pp. 1909-1927 ◽

Cited By ~ 86

Author(s):

Hadis Morkoç ◽

Roberto Cingolani ◽

Bernard Gil

Keyword(s):

Field Effect ◽

Semiconductor Device ◽

Field Effect Transistors ◽

Polarization Effects ◽

Device Structures ◽

Nitride Semiconductor ◽

And Performance

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Non-Destructive Measurements of III-V Semiconductor Device Structure by a Hard X-ray Microprobe

MRS Proceedings ◽

10.1557/proc-240-147 ◽

1991 ◽

Vol 240 ◽

Cited By ~ 3

Author(s):

F. Uchida ◽

J. Shigeta ◽

Y. SUZUKI

Keyword(s):

Semiconductor Device ◽

Film Structure ◽

Device Structure ◽

X Ray ◽

Model Sample ◽

Device Structures ◽

The Difference ◽

X Ray Absorption ◽

Non Destructive ◽

Non Destructive Characterization

ABSTRACTA non-destructive characterization technique featuring a hard X-ray Microprobe is demonstrated for lll-V semiconductor device structures. A GaAs FET with a 2 μm gate length is measured as a model sample of a thin film structure. X-ray scanning microscopic images of the FET are obtained by diffracted X-ray and fluorescence X-ray detection. Diffracted X-ray detection measures the difference in gate material and source or drain material as a gray level difference on the image due to the X-ray absorption ratio. Ni Ka fluorescence detection, on the other hand, provides imaging of 500 Å thick Ni layers, which are contained only in the source and drain metals, through non-destructive observation.

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Quantitative electron holographic tomography for the 3D characterisation of semiconductor device structures

Ultramicroscopy ◽

10.1016/j.ultramic.2008.05.014 ◽

2008 ◽

Vol 108 (11) ◽

pp. 1401-1407 ◽

Cited By ~ 38

Author(s):

Alison C. Twitchett-Harrison ◽

Timothy J.V. Yates ◽

Rafal E. Dunin-Borkowski ◽

Paul A. Midgley

Keyword(s):

Semiconductor Device ◽

Device Structures

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Optical properties of thin semiconductor device structures with reflective back-surface layers

10.1063/1.57813 ◽

1999 ◽

Cited By ~ 3

Author(s):

M. B. Clevenger ◽

C. S. Murray ◽

S. A. Ringel ◽

R. N. Sacks ◽

L. Qin ◽

...

Keyword(s):

Optical Properties ◽

Semiconductor Device ◽

Back Surface ◽

Surface Layers ◽

Device Structures ◽

Thin Semiconductor

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Interdiffusion in MBE-Grown Symmetrically and Asymmetrically Strained Si/Si1−xGex Superlattices Investigated by Ion Scattering

MRS Proceedings ◽

10.1557/proc-263-255 ◽

1992 ◽

Vol 263 ◽

Author(s):

B. Holländer ◽

R. Butz ◽

S. Mantl

Keyword(s):

Thermal Annealing ◽

Rapid Thermal Annealing ◽

Rutherford Backscattering Spectrometry ◽

Buffer Layers ◽

Arrhenius Law ◽

Ion Scattering ◽

Strained Si ◽

The Individual ◽

Interdiffusion Coefficients ◽

Fourier Algorithm

ABSTRACTThe interdiffusion in MBE-grown Si/Si1−xGex superlattices was measured by Rutherford backscattering spectrometry. The superlattices consisted of 5 periods of 100 !A Si and 100 !A Si1−xGex layers with Ge concentrations, x, between 0.20 and 0.70. Both, asymmetrically strained superlattices, grown on Si(100), as well as symmetrically strained superlattices, grown on relaxed Si1−y.Gey buffer layers were investigated. Rapid thermal annealing in the temperature range between 900°C and 1125°C leads to significant interdiffusion between the individual layers, indicated by a decrease of the amplitudes of the backscattering spectra. Interdiffusion coefficients were deduced using a Fourier algorithm. The interdiffusion coefficients follow an Arrhenius law for a given Ge concentration. The interdiffusivity increases significantly with increasing Ge concentration.

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