The Use of Superlattices to Block the Propagation of Dislocations in Semiconductors

1989 ◽  
Vol 148 ◽  
Author(s):  
A.E. Blakeslee
Keyword(s):  
Layer Thickness ◽  
Critical Thickness ◽  
Semiconductor Device ◽  
Growth Conditions ◽  
Buffer Layers ◽  
Effectiveness Factors ◽  
Dislocation Densities ◽  
Device Structures

ABSTRACTSince the discovery in 1973 that GaAs/GaAsP superlattices can be grown with low dislocation densities, considerable interest has developed in utilizing superlattices as dislocation filters in multilayer semiconductor device structures. Many attempts to implement this process have been described, with varying degrees of success being achieved. Some investigators have reported favorable results; some have observed no effect; and in some cases the situation was actually made worse. This paper analyzes these reports and attempts to clarify the confusion that has arisen. Suggestions are made for improved effectiveness. Factors considered include the strain between layers, the layer thickness, the concept of critical thickness, the dislocation geometry, and the influence of buffer layers and growth conditions.

Chirped Superlattices as Adjustable Strain Platforms for Metamorphic Semiconductor Devices

2018 ◽  
Vol 27 (01n02) ◽  
pp. 1840009
Author(s):  
Md Tanvirul Islam ◽  
Xinkang Chen ◽  
Tedi Kujofsa ◽  
John E. Ayers
Keyword(s):  
Lattice Constant ◽  
Semiconductor Device ◽  
Surface Strain ◽  
Buffer Layers ◽  
Individual Layer ◽  
Plane Lattice ◽  
Device Structures ◽  
Graded Layers ◽  
The Individual ◽  
Superlattice Period

Chirped superlattices are of interest as buffer layers in metamorphic semiconductor device structures, because they can combine the mismatch accommodating properties of compositionally-graded layers with the dislocation filtering properties of superlattices. Important practical aspects of the chirped superlattice as a buffer layer are the surface strain and surface in-plane lattice constant. In this work two basic types of InGaAs/GaAs chirped superlattice buffers have been studied. In design I (composition modulated), the average composition is varied by modulating the composition of one of the two layers in the superlattice period, but the individual layer thicknesses were fixed. In design II (thickness modulated), the individual layer thicknesses were modulated, but the compositions were fixed. In this paper the surface strain and surface in-plane lattice constant for these chirped superlattices are presented as functions of the top composition and period for each of these basic designs.

Characterisation of Thin Lattice Mismatched Heteroepitaxial Layers by XRD

1991 ◽  
Vol 240 ◽  
Author(s):  
Mary A. G. Halliwell
Keyword(s):  
Layer Thickness ◽  
Critical Thickness ◽  
Growth Conditions ◽  
Thin Layers ◽  
X Ray Diffraction ◽  
Rocking Curve ◽  
X Ray ◽  
Small Factor ◽  
Highly Strained ◽  
Heteroepitaxial Layers

ABSTRACTMany advanced III - V devices require highly strained heteroepitaxial layers less than 25 nm in thickness, with tight specifications on both the layer thickness and composition. In many cases the layers required are close to the critical thickness.The growth conditions for these thin layers are often extrapolated from established conditions for thicker layers. This method can result in layers which have the incorrect thickness and composition because of the transients which occur as growth commences. To minimise this problem it is desirable to establish growth conditions for layers which are as close to device requirements as possible. X-ray diffraction is capable of measuring layer thicknesses and compositions non-destructively. The minimum measurable layer thickness is usually within a small factor (typically 0.5 to 5 times) of device requirements.A single x-ray rocking curve is required to determine the thickness and composition of an unrelaxed (strained) layer. At least two rocking curves are required when relaxation is present. This paper discusses the appropriate choice of measurement conditions for a given sample.

Influence of MBE Growth Conditions on Dislocation Densities of GaAs/Ge Epilayers Grown on Silicon Substrates

1985 ◽  
Vol 43 ◽  
pp. 364-365
Author(s):  
K.M. Hones ◽  
P. Sheldon ◽  
B.G. Yacobi ◽  
A. Mason
Keyword(s):  
High Efficiency ◽  
Lattice Mismatch ◽  
Low Cost ◽  
Growth Conditions ◽  
Nonradiative Recombination ◽  
Device Structure ◽  
Si Substrates ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Dislocation Type

There is increasing interest in growing epitaxial GaAs on Si substrates. Such a device structure would allow low-cost substrates to be used for high-efficiency cascade- junction solar cells. However, high-defect densities may result from the large lattice mismatch (∼4%) between the GaAs epilayer and the silicon substrate. These defects can act as nonradiative recombination centers that can degrade the optical and electrical properties of the epitaxially grown GaAs. For this reason, it is important to optimize epilayer growth conditions in order to minimize resulting dislocation densities. The purpose of this paper is to provide an indication of the quality of the epitaxially grown GaAs layers by using transmission electron microscopy (TEM) to examine dislocation type and density as a function of various growth conditions. In this study an intermediate Ge layer was used to avoid nucleation difficulties observed for GaAs growth directly on Si substrates. GaAs/Ge epilayers were grown by molecular beam epitaxy (MBE) on Si substrates in a manner similar to that described previously.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Defect morphology in thick relaxed layers of InGaAs on GaAs

1990 ◽  
Vol 48 (4) ◽  
pp. 668-669
Author(s):  
R H Dixon ◽  
P Kidd ◽  
P J Goodhew
Keyword(s):  
Electron Microscopy ◽  
Surface Morphology ◽  
Growth Conditions ◽  
X Ray Diffraction ◽  
Double Crystal ◽  
Strained Layers ◽  
Good Surface ◽  
Transmission Electron ◽  
Device Structures ◽  
Surface Morphologies

Thick relaxed InGaAs layers grown epitaxially on GaAs are potentially useful substrates for growing high indium percentage strained layers. It is important that these relaxed layers are defect free and have a good surface morphology for the subsequent growth of device structures.3μm relaxed layers of InxGa1-xAs were grown on semi - insulating GaAs substrates by Molecular Beam Epitaxy (MBE), where the indium composition ranged from x=0.1 to 1.0. The interface, bulk and surface of the layers have been examined in planar view and cross-section by Transmission Electron Microscopy (TEM). The surface morphologies have been characterised by Scanning Electron Microscopy (SEM), and the bulk lattice perfection of the layers assessed using Double Crystal X-ray Diffraction (DCXRD).The surface morphology has been found to correlate with the growth conditions, with the type of defects grown-in to the layer (e.g. stacking faults, microtwins), and with the nature and density of dislocations in the interface.

Exciton dynamics in thick GaN MOVPE epilayers deposited on sapphire.

1997 ◽  
Vol 2 ◽  
Author(s):  
J. Allègre ◽  
P. Lefebvre ◽  
J. Camassel ◽  
B. Beaumont ◽  
Pierre Gibart
Keyword(s):  
Layer Thickness ◽  
Buffer Layers ◽  
Rate Equations ◽  
Time Resolved ◽  
Versus Layer ◽  
Level Model ◽  
Shallow Impurities ◽  
Aln Buffer ◽  
Time Resolved Photoluminescence

Time-resolved photoluminescence spectra have been recorded on three GaN epitaxial layers of thickness 2.5 μm, 7 μm and 16 μm, at various temperatures ranging from 8K to 300K. The layers were deposited by MOVPE on (0001) sapphire substrates with standard AlN buffer layers. To achieve good homogeneities, the growth was in-situ monitored by laser reflectometry. All GaN layers showed sharp excitonic peaks in cw PL and three excitonic contributions were seen by reflectivity. The recombination dynamics of excitons depends strongly upon the layer thickness. For the thinnest layer, exponential decays with τ ~ 35 ps have been measured for both XA and XB free excitons. For the thickest layer, the decay becomes biexponential with τ1 ~ 80 ps and τ2 ~ 250 ps. These values are preserved up to room temperature. By solving coupled rate equations in a four-level model, this evolution is interpreted in terms of the reduction of density of both shallow impurities and deep traps, versus layer thickness, roughly following a L−1 law.

TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching

2011 ◽  
Author(s):  
Liew Kaeng Nan ◽  
Lee Meng Lung
Keyword(s):  
Sample Preparation ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Critical Dimension ◽  
Low Energy ◽  
Ex Situ ◽  
Good Image Quality ◽  
Ion Beam Etching ◽  
Device Structures ◽  
Common Technique

Abstract Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.

Non-Destructive Measurements of III-V Semiconductor Device Structure by a Hard X-ray Microprobe

1991 ◽  
Vol 240 ◽  
Author(s):  
F. Uchida ◽  
J. Shigeta ◽  
Y. SUZUKI
Keyword(s):  
Semiconductor Device ◽  
Film Structure ◽  
Device Structure ◽  
X Ray ◽  
Model Sample ◽  
Device Structures ◽  
The Difference ◽  
X Ray Absorption ◽  
Non Destructive ◽  
Non Destructive Characterization

ABSTRACTA non-destructive characterization technique featuring a hard X-ray Microprobe is demonstrated for lll-V semiconductor device structures. A GaAs FET with a 2 μm gate length is measured as a model sample of a thin film structure. X-ray scanning microscopic images of the FET are obtained by diffracted X-ray and fluorescence X-ray detection. Diffracted X-ray detection measures the difference in gate material and source or drain material as a gray level difference on the image due to the X-ray absorption ratio. Ni Ka fluorescence detection, on the other hand, provides imaging of 500 Å thick Ni layers, which are contained only in the source and drain metals, through non-destructive observation.

Quantitative electron holographic tomography for the 3D characterisation of semiconductor device structures

2008 ◽  
Vol 108 (11) ◽  
pp. 1401-1407 ◽  
Author(s):  
Alison C. Twitchett-Harrison ◽  
Timothy J.V. Yates ◽  
Rafal E. Dunin-Borkowski ◽  
Paul A. Midgley
Keyword(s):  
Semiconductor Device ◽  
Device Structures
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