Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000820-000824 ◽  
Author(s):  
Jhin-Fang Huang ◽  
Wen Cheng Lai ◽  
Yong-Jhen Jiangn
Keyword(s):  
Communication Systems ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Process ◽  
Third Order ◽  
Chip Design ◽  
Chip Area ◽  
Rf Receiver ◽  
Front End ◽  
On Chip

An 1 V RF receiver front-end applying in 5.8 GHz DSRC (Dedicated Short Range Communication) systems is presented in this paper. The proposed chip includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The measured results of the chip show an input return loss of 20 dB, a conversion gain of 29 dB, a double-side band (DSB) noise figure (NF) of 5 dB, and a third-order intercept point (IIP3) of −24.4 dBm. The on-chip oscillator shows the measured tuning range of 5.17–5.98 GHz and phase noise of −118.5 dBc/Hz at 1 MHz offset from the 5.8 GHz carrier. The proposed receiver front-end is fabricated in a 0.18 μm CMOS process with a power consumption of 27.6 mW from a 1 V supply voltage. The chip area including PADs is 1.75 × 1.2 mm2.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

2013 ◽  
Vol 660 ◽  
pp. 113-118
Author(s):  
Jhin Fang Huang ◽  
Wen Cheng Lai ◽  
Kun Jie Huang ◽  
Ron Yi Liu
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Dual Mode ◽  
Chip Design ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area ◽  
Low Pass ◽  
Σδ Modulator

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2016 ◽  
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/℃ at range of -10 ℃ to 100 ℃, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 ℃. The chip area is 534 × 695 um^2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

scholarly journals Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

2019 ◽  
Vol 8 (2) ◽  
pp. 2406-2410
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Ultra Wide Band ◽  
Active Inductor ◽  
Cmos Process ◽  
Chip Area ◽  
Chip Size ◽  
Lna Design

An Ultra-Wide Band (UWB) Low Noise Amplifier (LNA) is affective in deciding the chip size and in the implementation cost at Radio Frequency applications. The proposed LNA design with an active inductor is a different solution to trounce the habit of passive inductors to cut the chip area. Designed in 90-nm CMOS process, a voltage gain of 9dB to 15.5dB for a supply voltage of 0.9v to 1.8V with a smallest Noise Figure (NF) of 5.7dB is achieved by the LNA, with low power utilization and at 2.40 GHz, with 345um2 of chip area.

scholarly journals Challenges in On-Chip Antenna Design and Integration With RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 43190-43204 ◽  
Author(s):  
Mahsa Keshavarz Hedayati ◽  
Abdolali Abdipour ◽  
Reza Sarraf Shirazi ◽  
Max J. Ammann ◽  
Matthias John ◽  
...  
Keyword(s):  
Communication Systems ◽  
Antenna Design ◽  
Rf Receiver ◽  
Nanoscale Cmos ◽  
Front End ◽  
On Chip Antenna ◽  
5G Communication ◽  
On Chip

scholarly journals CMOS low noise amplifiers for 1.575 GHz GPS applications

2009 ◽  
Vol 7 ◽  
pp. 145-150 ◽  
Author(s):  
M. Isikhan ◽  
A. Richter
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Performance Criteria ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Quality Factors ◽  
Voltage Range ◽  
Noise Amplifier ◽  
On Chip

Abstract. This paper presents Low Noise Amplifier (LNA) versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of 1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.

scholarly journals Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6118
Author(s):  
Abrar Siddique ◽  
Tahesin Samira Delwar ◽  
Prangyadarsini Behera ◽  
Manas Ranjan Biswal ◽  
Amir Haider ◽  
...  
Keyword(s):  
Noise Figure ◽  
High Gain ◽  
Common Source ◽  
Cmos Process ◽  
Third Order ◽  
Linear Coefficient ◽  
Chip Area ◽  
The Third ◽  
Fifth Generation ◽  
24 Ghz

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm2.

Resistorless Frequency Locked On-Chip Oscillator with Proportional-to-Absolute Temperature References

2019 ◽  
Vol 28 (10) ◽  
pp. 1950162 ◽  
Author(s):  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Voltage Sensitivity ◽  
Chip Area ◽  
Frequency Spread ◽  
Temperature Coefficient Of Frequency ◽  
On Chip

A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-[Formula: see text]m standard CMOS process with an active area of 0.072[Formula: see text]mm2. The temperature coefficient of frequency is 48[Formula: see text]ppm/∘C at best and 82.5[Formula: see text]ppm/∘C on average over [Formula: see text]–70∘C and the frequency spread is 1.43% ([Formula: see text]/[Formula: see text] without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65[Formula: see text]V to 1[Formula: see text]V and the power consumption is 95[Formula: see text]nW under the supply voltage of 0.65[Formula: see text]V.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

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