A Sub-1 V Temperature-Insensitive-PSR Bandgap Reference with Complementary Loop Locking

2019 ◽  
Vol 28 (03) ◽  
pp. 1950047 ◽  
Author(s):  
Guo-Cheng Huang ◽  
Hai-Gang Yang ◽  
Tao Yin ◽  
Xiao-Dong Xu ◽  
Yuan-Ming Zhu
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Temperature Coefficient ◽  
Power Supply ◽  
Room Temperature ◽  
Low Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Temperature Variations ◽  
Current Mirrors

This paper presents a novel low-voltage bandgap reference with improved power supply rejection (PSR). The proposed circuit adopts a complementary loop locking approach for stabilizing the drain-source voltages of the current mirrors, which gives rise to a boost of the PSR performance by more than 30[Formula: see text]dB over [Formula: see text]–110∘C and at 1-V supply. An analysis shows that the PSR of the proposed bandgap reference is typically characterized with its insensitivity to temperature variations. The circuit is designed with a commercial 0.18-[Formula: see text]m CMOS process. The experiment results of Monte Carlo simulation demonstrate that the average PSR with 1-V supply is [Formula: see text][Formula: see text]dB at DC and is [Formula: see text][Formula: see text]dB at 1[Formula: see text]kHz (attained under a room temperature condition of 27∘C). And the temperature coefficient of the DC-based PSR is about 0.83%/∘C at 1-V supply, significantly decreased by three–six folds compared to other conventional designs. The quiescent current consumed is only about 13.5[Formula: see text][Formula: see text]A.

A Curvature-Compensated, High Power Supply Rejection CMOS Bandgap Reference for MEMS Micro-Accelerometer

2011 ◽  
Vol 483 ◽  
pp. 481-486 ◽  
Author(s):  
Xiao Wei Liu ◽  
Bing Jun Lv ◽  
Peng Fei Wang ◽  
Liang Yin ◽  
Na Xu
Keyword(s):  
Temperature Coefficient ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Rejection Ratio ◽  
Compensation Technique ◽  
Supply Rejection

The reference is an important part in the accelerometer system. With the development of science and technology, the request of the performance of accelerometers is increasingly higher and the precision of reference directly affects the performance of accelerometers. Therefore, a reference voltage applicable to accelerometers is presented based on the analysis of basic principles of conventional bandgap reference (BGR) in this paper. A high-order curvature compensation technique, which uses a temperature dependent resistor ratio generated by a high poly resistor and a nwell resistor, effectively serves to reduce temperature coefficient of proposed reference voltage circuit and to a large extent improve its performance. To achieve a high power supply rejection ratio (PSRR) over a broad frequency range, a pre-regulator is introduced to remain the supply voltage of the core circuit of BGR relatively independent of the global supply voltage. The proposed circuitry is designed in standard 2.0μm CMOS process. The simulated result shows that the average temperature coefficient is less than 2ppm/°C in the temperature range from -40 to 120°C. The improvement on temperature coefficient (TC) is about 10 times reduction compared to the conventional approach. And the PSR at DC frequency and 1kHz achieves -107 and -71dB respectively at 9.0V supply voltage.

A Sub-1V High Precision CMOS Bandgap Reference

2013 ◽  
Vol 427-429 ◽  
pp. 1097-1100
Author(s):  
Qian Neng Zhou ◽  
Rong Xue ◽  
Hong Juan Li ◽  
Jin Zhao Lin ◽  
Yun Song Li ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Power Supply ◽  
Output Voltage ◽  
Supply Voltage ◽  
Piecewise Linear ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Compensation Technique ◽  
Simulation Results

In this paper, a low temperature coefficient bandgap voltage (BGR) is designed for A/D converter by adopting piecewise-linear compensation technique. The designed BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the PSRR of the designed BGR achieves-72.51dB, -72.49dB, and-70.58dB at 10Hz, 100Hz and 1kHz respectively. The designed BGR achieve the temperature coefficient of 1.57 ppm/°C when temperature is in the range from-35°C to 125°C. When power supply voltage VDD changes from 1V to 7V, the deviation of the designed BGR output voltage VREF is only 4.465μV.

A Bandgap Reference with Temperature Coefficient of 13.2 ppm/°C

2014 ◽  
Vol 981 ◽  
pp. 66-69
Author(s):  
Ming Yuan Ren ◽  
En Ming Zhao
Keyword(s):  
Power Supply ◽  
Process Simulation ◽  
Output Voltage ◽  
Operating Temperature ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Analysis Method ◽  
Operation Condition ◽  
Reference Circuit ◽  
Simulation Results

This paper presents a design and analysis method of a bandgap reference circuit. The Bandgap design is realized through the 0.18um CMOS process. Simulation results show that the bandgap circuit outputs 1.239V in the typical operation condition. The variance rate of output voltage is 0.016mV/°C? with the operating temperature varying from-60°C? to 160°C?. And it is 3.27mV/V with the power supply changes from 1.8V to 3.3V.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

Low Voltage FGMOS Four Quadrants Analog Multiplier

2014 ◽  
Vol 918 ◽  
pp. 313-318
Author(s):  
Jesús de la Cruz-Alejo ◽  
L. Noe Oliva-Moreno
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Low Voltage ◽  
Floating Gate ◽  
Cmos Process ◽  
Resistive Load ◽  
Analog Multiplier ◽  
Output Impedance ◽  
Cmos Transistors ◽  
Current Sensors

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

scholarly journals A Monte Carlo Simulation Platform for Studying Low Voltage Residential Networks

2014 ◽  
Vol 5 (6) ◽  
pp. 2766-2776 ◽  
Author(s):  
Ricardo Torquato ◽  
Qingxin Shi ◽  
Wilsun Xu ◽  
Walmir Freitas
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Low Voltage ◽  
Simulation Platform

A Statistical Simulation Model of Miner’s Rule

1981 ◽  
Vol 103 (2) ◽  
pp. 112-117 ◽  
Author(s):  
S. E. J. Johnsen ◽  
M. Doner
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Simulation Model ◽  
Fatigue Damage ◽  
Room Temperature ◽  
Statistical Simulation ◽  
Miner’S Rule ◽  
Cumulative Fatigue Damage ◽  
Miner's Rule ◽  
Monte Carlo Simulation Model

A Monte Carlo simulation model of the classical Miner’s rule for cumulative fatigue damage is devised and implemented for an example of three summands. Results from the simulation are compared with Miner’s rule. The concept of damage-sum-to-failure is developed and applied to measured values of INCO 901 at room temperature.

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