A New Floating Memristor Based on CBTA with Grounded Capacitors

2019 ◽  
Vol 28 (13) ◽  
pp. 1950217 ◽  
Author(s):  
Abdullah Yesil ◽  
Yunus Babacan ◽  
Fırat Kacar
Keyword(s):  
Integrated Circuit ◽  
Active Element ◽  
Supply Voltage ◽  
Bias Current ◽  
Analog Multiplier ◽  
Power Supply Voltage ◽  
Dc Power ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Memristor Emulator

This paper presents a new floating memristor emulator (FME) consisting of only a single current backward transconductance amplifier (CBTA) as the active element and two grounded capacitors. The proposed FME-based on CBTA enjoys some advantages that include minimum active and passive elements without using an analog multiplier circuit and grounded passive elements which are attractive for the integrated circuit. In addition, excluding the DC power supply voltage, it does not use bias voltage and/or bias current. The designed memristor circuit provides incremental and decremental characteristics without changing circuit topology or using a switching mechanism and it is implemented with a minimum of circuit elements. All simulation results for the memristor emulator were obtained as expected when compared with fabricated memristors.

New Grounded and Floating Memristor-Less Meminductor Emulators Using VDTA and CDBA

2021 ◽  
pp. 2150283
Author(s):  
Nisha Yadav ◽  
Shireesh Kumar Rai ◽  
Rishikesh Pandey
Keyword(s):  
Adaptive Learning ◽  
Hysteresis Loops ◽  
Cmos Technology ◽  
Chaotic Oscillator ◽  
Simulation Tool ◽  
Analog Multiplier ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Pinched Hysteresis

In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2[Formula: see text]MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180[Formula: see text]nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.

Floating Memristor and Inverse Memristor Emulators with Electronic Tuning

2021 ◽  
pp. 2150224
Author(s):  
Kapil Bhardwaj ◽  
Mayank Srivastava
Keyword(s):  
Active Element ◽  
The Other ◽  
Mathematical Properties ◽  
Process Technique ◽  
Transconductance Amplifier ◽  
Electronic Tuning ◽  
Memristor Emulator

The work reports two different configurations to emulate the floating memristor and inverse memristor behavior. The presented circuits are based on a modified concept of active element VDTA (Voltage Differencing Transconductance Amplifier) termed as MVDTA. The reported floating memristor employs only a single MVDTA and single grounded capacitance. On the other end, the floating emulation circuit of inverse memristor emulator is based on two MVDTAs and single grounded capacitance. The behavior of the realized element for both the configurations can be tuned electronically through biasing voltage. Also, there is no employment of any commercial IC or external circuitry for multiplication of analogue voltages which is generally required to implement memristive elements. Along with the circuit implementations, mathematical properties of ideal memristor and inverse memristor considering both symmetric as well as nonsymmetric models are discussed. All the emulation circuits are verified by executing simulations using CMOS 0.18[Formula: see text]um process technique under PSPICE environment. The reported circuits are also realized using commercially available IC LM13700 and results are presented.

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

Single Inductor Bipolar Outputs DC-DC Converter with Current Mode Control Circuit

2013 ◽  
Vol 534 ◽  
pp. 220-226 ◽  
Author(s):  
Nobukazu Takai ◽  
Takashi Okada ◽  
Kenji Takahashi ◽  
Hajime Yokoo ◽  
Shunsuke Miwa ◽  
...  
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Process ◽  
Power Supply Voltage ◽  
Negative Power ◽  
Current Mode Control ◽  
Mode Control ◽  
Digital Still Camera ◽  
Simulation Results

Mobile equipment such as organic-EL display, digital still camera and so on re-quire both positive and negative power supply voltage to obtain high quality. Single InductorMultiple-Output (SIMO) DC-DC converter can provide a pair of positive and negative outputvoltages with only one external inductor. This paper describes SIMO DC-DC Converter usingproposed current-mode control (CMC) circuit. The proposed CMC circuit realizes high responsespeed for the change of load current. Spectre simulations with 0.18m CMOS process parameterare performed to verify the validity of the proposed converter. The simulation results indicatethat the proposed converter has higher response time compared with conventional converter.

scholarly journals Low-voltage 0.35-/mi cmos wideband operational transconductance amplifier

2002 ◽  
Vol 15 (3) ◽  
pp. 361-369
Author(s):  
Lyes Bouzerara ◽  
Mohand Belaroussi
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Output Impedance ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Current Mirrors ◽  
Transconductance Amplifier ◽  
Cascade Structure ◽  
Feedback Frequency ◽  
High Output Impedance

A low voltage CMOS wideband operational Tran conductance amplifier (OTA) using regulated cascade structure with an active positive feedback frequency-dependent current mirrors and feed forward techniques, is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth, output impedance and phase margin enhancements. In this paper, an efficient implementation of a high output impedance current mirror is used in the design of an OTA by means of the regulated cascade circuits. This amplifier operates at ?1.25 V power supply voltage, exhibits a voltage gain of 68 dB, and provides a gain bandwidth product of 166 MHz. It drives a capacitive load of 1.6 pF and gives a power dissipation of 8.5 mW. The predicted performance is verified by simulations using HSPICE tool with 0.35 /itm CMOS TSMC parameters.

Modified current differencing transconductance amplifier – new versatile active element

2012 ◽  
Vol 60 (4) ◽  
pp. 739-750 ◽  
Author(s):  
A. Malcher
Keyword(s):  
Signal Processing ◽  
Active Element ◽  
Current Mode ◽  
Input Resistance ◽  
Analog Signal ◽  
Output Stage ◽  
Spice Simulation ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Current Differencing Transconductance Amplifier

Abstract This paper introduces a new current mode component called Modified Current Differencing Transconductance Amplifier (MCDTA). Important parameters of the circuit i.e. input resistance, z terminal resistance and transconductance of the output stage can be tuned electrically. The circuit can be implemented in linear and non-linear analog signal processing. The paper presents an example of the MCDTA application - a complete quadrature oscillator with the amplitude regulation. The functionality of the example circuit and its tuning capability were proved by the SPICE simulation results.

A wideband receiver front-end with low noise and high linearity by exploiting reconfigurable dual paths in 180 nm CMOS

2021 ◽  
pp. 2150210
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Lei Li ◽  
Wanting Zhou
Keyword(s):  
Duty Cycle ◽  
Noise Figure ◽  
Supply Voltage ◽  
Excitation Frequency ◽  
Low Noise ◽  
Resonance Structure ◽  
Front End ◽  
Main Path ◽  
Transconductance Amplifier ◽  
Simulation Results

In this paper, a wideband receiver front-end including the flexible reconfigurable main and auxiliary paths is proposed. Therein, the main path has the low-noise advantage thanks to the low-noise transconductance amplifier (LNTA) preceding the mixer and baseband. Meanwhile, by utilizing a mixer-first structure, the auxiliary path renders a high in-band and out-of-band linearity. Furthermore, an inductor resonance structure is also designed to mitigate the baseband noise crosstalk issue which is disclosed by a charging/discharging mechanism via the tail capacitance of passive mixers. Both of the receiving paths have shared a common baseband circuit while loading a commonly-shared 25% duty-cycle LO source generator. Simulation results by a 180 nm CMOS have demonstrated that the main path provides a low noise figure (NF) of 2.7 dB, while the auxiliary path obtains the in-band and out-of-band IIP3 of 9.2 and 21 dBm under typical LO excitation frequency of [Formula: see text] GHz. The power consumption of the main path of the dual-path front-end is 57 mW and that of the auxiliary path is 26 mW under a supply voltage of 1.8 V.

Mathematical framework for three cross-over memristor and its realization employing OTAs

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Kapil Bhardwaj ◽  
Mayank Srivastava
Keyword(s):  
Integrated Circuit ◽  
Design Methodology ◽  
Operating Conditions ◽  
Mathematical Framework ◽  
Simulation Environment ◽  
Content Type ◽  
Transconductance Amplifier ◽  
Multiple Cross ◽  
Memristor Emulator ◽  
First Time

Purpose The purpose of the paper is to report an emulation configuration of a three pinch-off memristor (TPM), whose transient characteristics consist three cross-over points on the voltage-current plane, which is dissimilar to a conventional memristor. These characteristics can be very useful in memristor-based multi-bit memory devices and hyperchaotic oscillators. Design/methodology/approach The work describes the Mathematical framework for TPM and a circuit emulator based on the derived conditions. The configuration is based on five operational transconductance amplifier (OTAs) and four grounded passive elements. After which, we have verified its operation using personal simulation program with integrated circuit emphasis simulation environment. Finally, the implementation of OTA-based TPM using commercial integrated circuit (IC) LM13700 has also been presented. Findings It has been shown that a flux-dependent memductance expression of cubic order can show three intersections on the VI contour under certain parameter related constraints. Moreover, the OTA-based emulator reported in the work is very compact in nature because of the no use of external multiplier IC/circuitry, which has been popular in previous emulators. Originality/value For the first time, a multiple cross-over memristor emulator has been reported which can operate under practical operating conditions such as at practical operating frequencies and sinusoidal excitation.

Analog Integrated Circuit Optimization

2020 ◽  
pp. 95-130
Author(s):  
Houda Daoud ◽  
Dalila Laouej ◽  
Jihene Mallek ◽  
Mourad Loulou
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Pso Algorithm ◽  
Circuit Optimization ◽  
Ultra Low Power ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Threshold Voltages ◽  
Dc Gain ◽  
Low Threshold

This chapter presents a novel telescopic operational transconductance amplifier (OTA) using the bulk-driven MOS technique. This circuit is optimized for ultra-low power applications such as biomedical devices. The proposed the bulk-driven fully differential telescopic OTA with very low threshold voltages is designed under ±0.9V supply voltage. Thanks to the particle swarm optimization (PSO) algorithm, the circuit achieves high performances. The OTA simulation results present a DC gain of 63.6dB, a GBW of 2.8MHz, a phase margin (PM) of 55.8degrees and an input referred noise of 265.3nV/√Hz for a low bias current of 52nA.

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