A 4-Stage Pipelined Architecture for Point Multiplication of Binary Huff Curves

2020 ◽  
Vol 29 (11) ◽  
pp. 2050179 ◽  
Author(s):  
Muhammad Rashid ◽  
Malik Imran ◽  
Atif Raza Jafri ◽  
Zahid Mehmood
Keyword(s):  
Critical Path ◽  
Mathematical Formulation ◽  
Area Ratio ◽  
Design Tool ◽  
Clock Frequency ◽  
Point Multiplication ◽  
Area Reduction ◽  
Pipelined Architecture ◽  
Two Factors ◽  
Time Required

This work has proposed a 4-stage pipelined architecture to achieve an optimized throughput over area ratio for point multiplication (PM) computation in binary huff curves (BHC) cryptography. The original mathematical formulation of BHC is revisited with an objective to reduce the required area. Consequently, a simplified formulation of BHC is obtained with 43% reduction in the hardware resources. As far as the throughput is concerned, it is improved first by reducing the critical path and second by minimizing the number of clock cycles (CCs) required to compute one PM. The critical path is reduced through the placement of pipeline registers, whereas the number of required CCs are minimized through an efficient scheduling of computations. These two factors i.e., the area reduction and throughput optimizations, have resulted in maximizing the throughput over area ratio. The proposed pipelined architecture is implemented over [Formula: see text] field, using standard NIST curve parameters. The architecture is modeled in Verilog and synthesized using Xilinx (ISE 14.7) design tool on Virtex 7 FPGA. The implementation results show that 17% improvement in clock frequency, 13% reduction in the time required to compute one PM and 2.6% improvement in throughput/area are achieved when compared with the most recent state of the art solutions.

scholarly journals Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-18 ◽  
Author(s):  
Deepa Yagain ◽  
A. Vijaya Krishna
Keyword(s):  
Digital Filter ◽  
Computer Aided Design ◽  
Performance Metrics ◽  
Filter Design ◽  
Critical Path ◽  
Computation Time ◽  
Design Tool ◽  
High Level Synthesis ◽  
Clock Frequency ◽  
High Level

Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

scholarly journals A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2698
Author(s):  
Muhammad Rashid ◽  
Mohammad Mazyad Hazzazi  ◽  
Sikandar Zulqarnain Khan ◽  
Adel R. Alharbi  ◽  
Asher Sajid  ◽  
...  
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
State Of The Art ◽  
Critical Path ◽  
Clock Frequency ◽  
Description Language ◽  
Point Multiplication ◽  
Low Area ◽  
Field Programmable ◽  
Hardware Description

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

Rancang Bangun Alat Olahan Minyak Kelapa

2016 ◽  
Vol 10 (1) ◽  
pp. 70-77
Author(s):  
Jantri Sirait ◽  
Sulharman Sulharman
Keyword(s):  
Electric Motor ◽  
Performance Test ◽  
Production Capacity ◽  
Coconut Oil ◽  
Heating Time ◽  
Design Tool ◽  
Coconut Milk ◽  
Heating Process ◽  
And Performance ◽  
Time Required

Has done design tool is a tool of refined coconut oil coconut grater, squeezer coconut milk and coconut oil heating, with the aim to streamline the time of making coconut oil and coconut oil increase production capacity. The research method consists of several stages, among others; image creation tool, procurement of materials research, cutting the material - the material framework of tools and performance test tools. The parameters observed during the performance test tools is time grated coconut, coconut milk bleeder capacity, the capacity of the boiler and the heating time of coconut oil. The design tool consists of three parts, namely a tool shaved coconut, coconut milk wringer and coconut milk heating devices. Materials used for the framework of such tools include iron UNP 6 meters long, 7.5 cm wide, 4 mm thick, while the motor uses an electric motor 0.25 HP 1430 rpm and to dampen the rotation electric motor rotation used gearbox with a ratio of round 1 : 60. the results of the design ie the time required for coconut menyerut average of 297 seconds, coconut milk wringer capacity of 5 kg of processes and using gauze pads to filter coconut pulp, as well as the heating process takes ± 2 hours with a capacity of 80 kg , The benefits of coconut oil refined tools are stripping time or split brief coconut average - average 7 seconds and coconut shell can be used as craft materials, processes extortion coconut milk quickly so the production capacity increased and the stirring process coconut oil mechanically.ABSTRAKTelah dilakukan rancang bangun alat olahan minyak kelapa yaitu alat pemarut kelapa, pemeras santan kelapa dan pemanas minyak kelapa, dengan tujuan untuk mengefisiensikan waktu pembuatan minyak kelapa serta meningkatkan kapasitas produksi minyak kelapa. Metode penelitian terdiri dari beberapa tahapan antara lain; pembuatan gambar alat, pengadaan bahan-bahan penelitian, pemotongan bahan - bahan rangka alat dan uji unjuk kerja alat. Parameter yang diamati pada saat uji unjuk kerja alat adalah waktu parut kelapa, kapasitas pemeras santan kelapa, kapasitas tungku pemanas serta waktu pemanasan minyak kelapa. Rancangan alat terdiri dari tiga bagian yaitu alat penyerut kelapa, alat pemeras santan kelapa dan alat pemanas santan kelapa. Bahan yang dipergunakan untuk rangka alat tersebut  yaitu besi UNP panjang 6 meter, lebar 7,5 cm, tebal 4 mm, sedangkan untuk motor penggerak menggunakan motor listrik 0,25 HP 1430 rpm dan untuk meredam putaran putaran motor listrik dipergunakan gearbox  dengan perbandingan putaran 1 : 60. Hasil dari rancangan tersebut yaitu waktu yang dibutuhkan untuk menyerut kelapa rata-rata 297 detik, kapasitas alat pemeras santan kelapa 5 kg sekali proses dan menggunakan kain kassa untuk menyaring ampas kelapa, serta Proses pemanasan membutuhkan waktu ± 2 jam dengan kapasitas 80 kg. Adapun keunggulan alat olahan minyak kelapa ini adalah waktu pengupasan atau belah kelapa singkat rata – rata 7 detik dan tempurung kelapa dapat digunakan sebagai bahan kerajinan, proses pemerasan santan kelapa cepat sehingga kapasitas produksi meningkat dan proses pengadukan minyak kelapa secara mekanis. Kata kunci : penyerut, pemeras, pemanas,minyak kelapa,olahan minyak kelapa.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

2019 ◽  
Vol 28 (09) ◽  
pp. 1950149
Author(s):  
Bahram Rashidi ◽  
Mohammad Abedini
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Path Delay ◽  
Point Multiplication ◽  
Low Area ◽  
Elliptic Curve Cryptosystems ◽  
Edwards Curves ◽  
Special Cases ◽  
Field Multiplication

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

scholarly journals Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Ali Asghar ◽  
Muhammad Mazher Iqbal ◽  
Waqar Ahmed ◽  
Mujahid Ali ◽  
Husain Parvez ◽  
...  
Keyword(s):  
High Performance ◽  
Critical Path ◽  
Path Delay ◽  
Gate Arrays ◽  
Area Reduction ◽  
Area Overhead ◽  
Logic Block ◽  
Field Programmable ◽  
Boolean Matching ◽  
Programmable Gate Arrays

In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.

SIMULTANEOUS RADIOIMMUNOASSAY OF LUTEINIZING HORMONE AND FOLLICLE-STIMULATING HORMONE

1978 ◽  
Vol 79 (3) ◽  
pp. 407-408 ◽  
Author(s):  
M. J. ELLIS ◽  
R. A. DONALD ◽  
J. H. LIVESEY
Keyword(s):  
Luteinizing Hormone ◽  
Follicle Stimulating Hormone ◽  
Significant Proportion ◽  
Chorionic Gonadotrophin ◽  
Human Chorionic Gonadotrophin ◽  
Operating Costs ◽  
Two Factors ◽  
And Performance ◽  
Time Required ◽  
Stimulating Hormone

The Medical Unit, The Princess Margaret Hospital, Christchurch 2, New Zealand (Revised manuscript received 21 August 1978) The frequent clinical and research requirement for measurement of both plasma luteinizing hormone (LH) and follicle-stimulating hormone (FSH) has prompted the development of a simultaneous radioimmunoassay for these two hormones. The considerable advantages of a simultaneous method include an economy of plasma volume, assay reagents, test-tubes and, more importantly, the time required for radioactive counting and performance of the assay by technical staff. The latter two factors comprise a significant proportion of radioimmunoassay operating costs. This report describes a simultaneous radioimmunoassay based on the use of 131I-labelled FSH, 125I-labelled LH, anti-FSH serum M93 6873 (a generous gift from Professor W. R. Butt, Birmingham), anti-human chorionic gonadotrophin (HCG) serum for LH measurement (Donald, 1972) and donkey anti-rabbit precipitating serum (Wellcome Reagents, U.K.) for separation of antibody-bound and free hormones. Pituitary gonadotrophin standard (LER 907)

scholarly journals Removal Methods Assessment Through Reduction Algae Count in Uncovered Water Tank

2018 ◽  
Vol 7 (4.20) ◽  
pp. 200
Author(s):  
Nesrin Jassim Al- Mansori ◽  
Saif Al deen ali klakeel
Keyword(s):  
Rotational Speed ◽  
Rotation Speed ◽  
The Other ◽  
Water Tank ◽  
Green Growth ◽  
Algae Removal ◽  
Two Factors ◽  
Time Required ◽  
Biological Methods ◽  
The Cost

The research includes study the effect of three factors (voltage, rotational speed, acidity) with time to remove or reduce the percentage of algae in uncovered water tank; these factors studied combined with each other or individually. the removal percentage of algae increased by increasing the electrical voltage, Best result of removal was obtained when using two factors, change in the voltage (4, 8,12 and 16) vole /cm and speed of rotation (50, 100, 150 and 200) rpm . The rate of removal of algae was 100% at voltage 16 volts with a rotation speed (200) rpm and 40 min.   The values extracted for algae removal showed that the best result was (100%) at (voltage 16 vole/cm and acidity with pH 4) with time 30 min. It can be conclude, the best method to remove or reduction of algae in uncovered tanks was physical one as a compared with the other methods like chemical or biological methods. Therefore, it needs additional requirements unlike physical strategies decrease, the cost and time required to evacuate green growth. 

scholarly journals A Cradle-to-Grave Carbon Index (CI) for Design, Construction and Operations of Site-Specific Buildings

2019 ◽  
Vol 111 ◽  
pp. 03057
Author(s):  
Boggarm Setty ◽  
James Woods
Keyword(s):  
Design Tool ◽  
Energy Utilization ◽  
Impact Factors ◽  
Construction Operations ◽  
Site Specific ◽  
Floor Area ◽  
Design Alternatives ◽  
Two Factors ◽  
Sum Of Products ◽  
Design Construction

During the 1970s, the Energy Utilization Index (EUI) was introduced in terms of the annual rate of energy used per unit of floor area in site-specific buildings. It indicates energy but not total resource use effectiveness of design alternatives compared to baseline values (i.e., targets). Because of increasing concerns about indoor and outdoor emissions from carbon-based products and processes, an analogous “Carbon Index” (CI) is here introduced as a cradle-tograve design tool for evaluating the performance of design alternatives in terms of carbon emitted throughout the five stages of a building’s lifespan: siting, design, construction, operations, and demolition/recycling. This CI is expressed as equivalent mass of CO2 per unit floor area (CO2e). At each stage, this CI is determined as the sum-of-products of two factors: 1) “Primary Factors” (PF), scalars that are defined and quantified by the designer; and 2) “Carbon Impact Factors” (CIF), which are standardized 2x1 matrices that characterize the PFs in terms of “embodied” CO2e emissions in the materials, assemblies, and equipment that are installed in the building, and as CO2e emissions that are released during the “operations” of the building. This design tool is posited to foster more accurate calculations of carbon emissions for design alternatives.

Stimulus-Response Incompatibility: Extra Processing Stages versus Response Competition

1979 ◽  
Vol 23 (1) ◽  
pp. 415-419
Author(s):  
Steven P. Rogers
Keyword(s):  
Processing Time ◽  
Response Competition ◽  
Reaction Times ◽  
Stimulus Response ◽  
Compatibility Factor ◽  
Two Factors ◽  
Additive Factor Method ◽  
Time Required ◽  
The Relationship ◽  
Spatial Stroop

The extra processing time required by incompatible S-R arrays has been explained in two ways: an increased number of processing stages or response competition from the compatible response. The additive factor method was employed, combining an S-R compatibility factor with a known response competition factor (a spatial Stroop task). The relationship between these two factors was shown to be an additive one, indicating that the two variables have their loci in (at least) two separate stages. This outcome is seen as persuasive evidence that longer reaction times for incompatible responses result from extra processing stages, rather than from response competition.

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