Processing Electrocardiographic Signals using a Custom Designed Sigma-Delta Modulator

2021 ◽  
pp. 2250040
Author(s):  
Juan J. Ocampo-Hidalgo ◽  
Javier Alducin-Castillo ◽  
Jesus E. Molinar-Solis
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Low Complexity ◽  
Cmos Technology ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Silicon Area ◽  
Electrocardiographic Signal ◽  
The Time Domain ◽  
Oversampling Ratio

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator’s output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66[Formula: see text]dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5[Formula: see text]V, exhibits a power consumption of 38[Formula: see text][Formula: see text]W, and uses a silicon area of 0.052[Formula: see text]mm2, it is suitable for single battery-operated systems on a chip.

scholarly journals Second-order sigma-delta modulator in standard cmos technology

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Second Order ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Power Meter ◽  
Sampling Ratio

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.

scholarly journals Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool

2015 ◽  
Vol 63 (4) ◽  
pp. 919-922 ◽  
Author(s):  
P. Śniatała ◽  
M. Naumowicz ◽  
A. Handkiewicz ◽  
S. Szczęsny ◽  
J.L.A. de Melo ◽  
...  
Keyword(s):  
Current Mode ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Mode Structure ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Current Output ◽  
Image Pixels ◽  
Time Loop ◽  
A Current

Abstract The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.

A multirate Sigma Delta modulator for GSM standard in CMOS technology

2009 NORCHIP ◽  
2009 ◽  
Author(s):  
M. Laguna ◽  
R. Viladoms ◽  
F. Colodro ◽  
A. Torralba
Keyword(s):  
Cmos Technology ◽  
Sigma Delta Modulator ◽  
Sigma Delta

AN EFFICIENT LOW-POWER SIGMA-DELTA MODULATOR FOR MULTI-STANDARD WIRELESS APPLICATIONS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Cmos Technology ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Design And Implementation ◽  
Simulation Results ◽  
System Level Simulations

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.

scholarly journals Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Tareq Hasan Khan ◽  
Khan A. Wahid
Keyword(s):  
Low Power ◽  
Compression Ratio ◽  
Low Complexity ◽  
Cmos Technology ◽  
Silicon Area ◽  
Endoscopic Images ◽  
Prediction Scheme ◽  
Image Pixels ◽  
Image Compressor ◽  
Wireless Capsule

We present a lossless and low-complexity image compression algorithm for endoscopic images. The algorithm consists of a static prediction scheme and a combination of golomb-rice and unary encoding. It does not require any buffer memory and is suitable to work with any commercial low-power image sensors that output image pixels in raster-scan fashion. The proposed lossless algorithm has compression ratio of approximately 73% for endoscopic images. Compared to the existing lossless compression standard such as JPEG-LS, the proposed scheme has better compression ratio, lower computational complexity, and lesser memory requirement. The algorithm is implemented in a 0.18 μm CMOS technology and consumes 0.16 mm × 0.16 mm silicon area and 18 μW of power when working at 2 frames per second.

A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope

2013 ◽  
Vol 562-565 ◽  
pp. 369-373 ◽  
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Song Chen ◽  
Peng Fei Wang ◽  
Xiao Wei Liu
Keyword(s):  
Signal To Noise Ratio ◽  
System Simulation ◽  
Sampling Frequency ◽  
Effective Number ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
High Bandwidth ◽  
Oversampling Ratio ◽  
Input Level

In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes overload.

scholarly journals Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6552
Author(s):  
Juan B. Talens ◽  
Jose Pelegri-Sebastia ◽  
Maria Jose Canet
Keyword(s):  
Gas Sensor ◽  
Low Voltage ◽  
Low Cost ◽  
Low Complexity ◽  
System On Chip ◽  
Working Environment ◽  
Sigma Delta ◽  
Sensor Applications ◽  
Analog Signals ◽  
On Chip

Analog signals from gas sensors are used to recognize all types of VOC (Volatile Organic Compound) substances, such as toxic gases, tobacco or ethanol. The processes to recognize these substances include acquisition, treatment and machine learning for classification, which can all be efficiently implemented on a Field Programmable Gate Array (FPGA) aided by Low-Voltage Differential Signaling (LVDS). This article proposes a low-cost 11-bit effective number of bits (ENOB) sigma-delta Analog to Digital Converter (ADC), with an SNR of 75.97 dB and an SFDR of 72.28 dB, whose output is presented on screen in real time, thanks to the use of a Linux System on Chip (SoC) system that enables parallelism, high-level programming and provides a working environment for the scientific treatment of gas sensor signals. The high frequency achieved by the implemented ADC allows for multiplexing the capture of several analog signals with an optimal resolution. Additionally, several ADCs can be implemented in the same FPGA so several analog signals can be digitalized in parallel.

scholarly journals An Interface ASIC for MEMS Vibratory Gyroscopes with Nonlinear Driving Control

Micromachines ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 270 ◽  
Author(s):  
Risheng Lv ◽  
Qiang Fu ◽  
Liang Yin ◽  
Yuan Gao ◽  
Wei Bai ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Resonance Oscillation ◽  
Temperature Drift ◽  
Sigma Delta ◽  
Vibratory Gyroscopes ◽  
Digital Circuitry ◽  
Mems Vibratory Gyroscopes

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm2. Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range.

The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator

2012 ◽  
Vol 433-440 ◽  
pp. 5727-5732
Author(s):  
Jun Han ◽  
Wei Dong Wang
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Optimization Technique ◽  
Cmos Technology ◽  
Switched Capacitor ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Transconductance Amplifier ◽  
A Chain

This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

2013 ◽  
Vol 22 (09) ◽  
pp. 1340012
Author(s):  
KAREN WAN ◽  
GIGI CHAN ◽  
WILLIAM WONG ◽  
KAM CHUEN WAN ◽  
BRYCE YAU ◽  
...  
Keyword(s):  
Fourth Order ◽  
Cmos Technology ◽  
Second Order ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Digital Conversion ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Analog To Digital Conversion

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

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