A LARGE-SWING HIGH-DRIVE CMOS BUFFER AMPLIFIER FOR A WIDE LOAD RANGE

1992 ◽  
Vol 02 (04) ◽  
pp. 323-333 ◽  
Author(s):  
NAVID YAZDI ◽  
M. AHMADI ◽  
G.A. JULLIEN ◽  
M. SHRIDHAR
Keyword(s):  
Harmonic Distortion ◽  
Cmos Technology ◽  
Good Stability ◽  
Output Stage ◽  
Load Range ◽  
High Drive ◽  
Wide Range ◽  
Buffer Amplifier ◽  
Resistive Loads ◽  
Output Swing

A high-swing, high-drive CMOS buffer amplifier, with good stability over a wide range of capacitive and resistive loads, is presented in this paper. A new area efficient output stage with a relatively small compensation capacitor has been used so that the circuit occupies only 120 mils2 in a 3 μm CMOS technology. The buffer has a drive capability of 110 kHz into a 5000 pF load with a rail-to-rail output swing for load resistances greater than 10 kΩ and acceptable total harmonic distortion with loads down to 270 Ω.

A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

2007 ◽  
Vol 16 (04) ◽  
pp. 627-639 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
WEERACHAI NAKHLO
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Common Source ◽  
Output Stage ◽  
Circuit Performance ◽  
Rail To Rail ◽  
Source Follower ◽  
Transfer Error

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

scholarly journals A Controllable Constant Power Generator in 0.35 μm CMOS Technology for Thermal-Based Sensor Applications

2018 ◽  
Vol 2018 ◽  
pp. 1-12
Author(s):  
Milena Zogović Erceg
Keyword(s):  
Relative Error ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Load Resistance ◽  
Cmos Technology ◽  
Constant Power ◽  
Power Generator ◽  
Sensor Applications ◽  
Wide Range ◽  
Resistive Loads

A CMOS controllable constant power generator based on multiplier/divider circuit is presented. It generates constant power for a wide range of the resistive loads. For the generated power of 5 mW, and the resistance range from 0.5 kΩ to 1.5 kΩ, the relative error of dissipated power is less than 0.6%. For single supply voltage of 5 V, presented controllable constant power generator generates power from 0.5 mW to 7.8 mW, for the load resistance dynamic range from 3 up to 15, while the relative error of generated power is less than 2%. The frequency bandwidth of the proposed design is up to 5 MHz. Through the detailed analysis of the loop gain, it is shown that the circuit has no stability problems.

scholarly journals A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

2011 ◽  
Vol 8 (15) ◽  
pp. 1245-1251 ◽  
Author(s):  
Ching-Che Chung ◽  
Duo Sheng ◽  
Sung-En Shen
Keyword(s):  
Duty Cycle ◽  
Cmos Technology ◽  
Phase Alignment ◽  
Wide Range

OPTIMIZATION OF GAS-DIESEL ENGINE REGULATION AS A METHOD OF IMPROVING ITS ECOLOGICAL CHARACTERISTICS

2021 ◽  
pp. 28-32
Author(s):  
VALERIY L. CHUMAKOV ◽  
Keyword(s):  
Carbon Monoxide ◽  
Diesel Engine ◽  
Nitrogen Oxides ◽  
Diesel Fuel ◽  
Hydrocarbon Fuel ◽  
Load Range ◽  
Engine Operation ◽  
Exhaust Gases ◽  
Wide Range ◽  
Diesel Cycle

The paper shows some ways to improve the environmental characteristics of a diesel engine using gaseous hydrocarbon fuel and operating the engine in a gas-diesel cycle mode. Some possibilities to reduce toxic components of exhaust gases in a gas-diesel engine operating on liquefi ed propane-butane mixtures have been studied. Experiments carried out in a wide range of load from 10 to 100% and speed from 1400 to 2000 rpm showed that the gas-diesel engine provides a suffi ciently high level of diesel fuel replacement with gas hydrocarbon fuel. The authors indicate some eff ective ways to reduce the toxicity of exhaust gases. The engine power should be adjusted by the simultaneous supply of fuel, gas and throttling the air charge in the intake manifold. This method enriches the fi rst combusting portions to reduce nitrogen oxides and maintains the depletion of the main charge within the fl ammability limits of the gas-air charge to reduce carbon monoxide and hydrocarbons. The authors found that when the engine operates in a gas-diesel cycle mode, the power change provides a decrease in nitrogen oxide emissions of gas-diesel fuel only due to gas supply in almost the entire load range as compared to the pure diesel. At high loads (more than 80%) stable engine operation is ensured up to 90% of diesel fuel replaced by gas. Even at 10% of diesel fuel used the concentration of nitrogen oxides decreases by at least 15…20% as compared with a diesel engine in the entire load range. However, there is an increased emission of hydrocarbons and carbon monoxide in the exhaust gases. Further experimental studies have shown that optimization of the gas diesel regulation can reduce the mass emission of nitrogen oxides contained in exhaust gases in 2…3 times and greatly reduce the emission of incomplete combustion products – carbon monoxide and hydrocarbons.

HIGH-SLEW RATE LOW-QUIESCENT CURRENT RAIL-TO-RAIL CMOS BUFFER AMPLIFIER FOR FLAT PANEL DISPLAYS

2011 ◽  
Vol 20 (07) ◽  
pp. 1277-1286 ◽  
Author(s):  
MERIH YILDIZ ◽  
SHAHRAM MINAEI ◽  
EMRE ARSLAN
Keyword(s):  
Power Supply ◽  
Monte Carlo Analysis ◽  
Cmos Process ◽  
Flat Panel Displays ◽  
Slew Rate ◽  
Flat Panel ◽  
Output Stage ◽  
Rail To Rail ◽  
Buffer Amplifier ◽  
Quiescent Current

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

scholarly journals Domino Sense Analogous Contradict Planning of A CMOS

2019 ◽  
Vol 8 (6S2) ◽  
pp. 261-264
Keyword(s):  
Cmos Technology ◽  
Vlsi Circuits ◽  
Domino Logic ◽  
Flip Flop ◽  
Cell Library ◽  
Dynamic Circuits ◽  
Wide Range ◽  
Pipeline Segment

The fundamental target of this paper comprises of the domino rationale way and checking path. A fast wide range parallel contradicts that accomplishes high working frequencies throughout an account pipeline segment demeanor utilizing just three undemanding redundant CMOS-rationale module types. The three essential module types are isolated by D flip failure. The three element types are set in an exceedingly dull constitution in the tallying way and Domino Logic way. Enthusiastic domino rationale circuits are broadly utilized in present day computerized VLSI circuits. These dynamic circuits are utilized in superior structures. Along these lines simultaneously refreshing the tally state with a consistent deferral at all tallying way module regarding the clock edge. This construction is versatile to self-assertive portion counter widths utilizing just the three module types. The deferral counter is contained the underlying module admittance times only, three-info AND-entryway delay and a D-type flip-flop. The motivation behind the project is to diminish the Power utilization and CMOS Technology in the counter way and Domino rationale way by utilizing DSCH in Microwind Tool. The proposed Counter way is structured utilizing 0.10µm TSMC Digital cell library and its expended 0.215mW.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

A novel tunable gain CMOS buffer amplifier for large resistive loads

Integration ◽  
2021 ◽  
Vol 77 ◽  
pp. 1-12
Author(s):  
Jayachandran Remya ◽  
P.C. Subramaniam ◽  
K.J. Dhanaraj
Keyword(s):  
Buffer Amplifier ◽  
Resistive Loads

scholarly journals Design of a Class-D Audio Amplifier With Analog Volume Control for Mobile Applications

2016 ◽  
Vol 62 (2) ◽  
pp. 187-196
Author(s):  
Karim El khadiri ◽  
Hassan Qjidaa
Keyword(s):  
Power Efficiency ◽  
High Efficiency ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Volume Control ◽  
Ramp Generator ◽  
Audio Amplifier ◽  
Class D ◽  
Level Shifter ◽  
Programmable Gain

Abstract A class-D audio amplifier with analog volume control (AVC) for portable applications is proposed in this paper. The proposed class-D consist of two sections. First section is an analog volume control which consists of an integrator, an analog MUX and a programmable gain amplifier (PGA). The AVC is implemented with three analog inputs (Audio, Voice, FM). Second section is a driver which consists of a ramp generator, a comparator, a level shifter and a gate driver. The driver is designed to obtain a low distortion and a high efficiency. Designed with 0.18 um 1P6M CMOS technology, the class-D audio amplifier with AVC achieves a total root-mean-square (RMS) output power of 0.5W, a total harmonic distortion plus noise (THD+N) at the 8-Ω load less than 0.06% and a power efficiency of 90% with a total area of 1.74 mm2.

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