A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

2007 ◽  
Vol 16 (04) ◽  
pp. 627-639 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
WEERACHAI NAKHLO
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Common Source ◽  
Output Stage ◽  
Circuit Performance ◽  
Rail To Rail ◽  
Source Follower ◽  
Transfer Error

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

2016 ◽  
Vol 25 (08) ◽  
pp. 1650084 ◽  
Author(s):  
Liang Zhang ◽  
Dengquan Li ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Common Source ◽  
Digital Converter ◽  
Input Buffer ◽  
Analog To Digital ◽  
Source Follower ◽  
Time Interleaved

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

High Frequency Unity Gain Buffer in 90-nm CMOS Technology

2016 ◽  
Vol 25 (07) ◽  
pp. 1650071
Author(s):  
Shuo Li ◽  
Xiaomeng Zhang ◽  
Saiyu Ren
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Common Source ◽  
Active Load ◽  
Cmos Design ◽  
Saturation Region ◽  
Unity Gain ◽  
Unity Gain Buffer ◽  
Voltage Swing

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

scholarly journals A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3303
Author(s):  
Jacek Jakusz ◽  
Waldemar Jendernalik ◽  
Grzegorz Blakiewicz ◽  
Miron Kłosowski ◽  
Stanisław Szczepański
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Channel Length ◽  
Temperature Drift ◽  
Nanometer Cmos ◽  
Rail To Rail ◽  
Transconductance Amplifier ◽  
Current Converter ◽  
Linearity Error

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

Feedforward Bulk-Driven Class AB Fully-Differential Second-Generation Current Conveyor (FDCCII)

2014 ◽  
Vol 979 ◽  
pp. 62-65
Author(s):  
Thawatchai Thongleam ◽  
Varakorn Kasemsuwan
Keyword(s):  
Second Generation ◽  
Transfer Characteristic ◽  
Cmos Technology ◽  
Circuit Performance ◽  
Input Stage ◽  
Class Ab ◽  
Fully Differential ◽  
Rail To Rail ◽  
Differential Pair ◽  
Dc Current

In this paper, a feedforward bulk-driven class AB fully-differential second-generation current conveyer (FDCCII) is presented. Bulk-driven differential pair is employed for the input stage allowing the FDCCII to operate with rail-to-rail operation. Feedfoward technique is also incorporated into input stage to increase the DC gain and minimize the common mode gain. The circuit performance is verified using HSPICE in 0.18 μm CMOS technology. The simulation results show rail-to-rail input and output swings. The DC voltage transfer characteristic between ports Y and X and DC current transfer characteristic between ports X and Z shows good linearity. The bandwidths show 25.7 MHz (VX/VY), 30 MHz (IZ/IX), respectively. The power dissipation is 267.5 μW.

FULLY PROGRAMMABLE UNIVERSAL FILTER WITH INDEPENDENT GAIN-ω0-Q CONTROL BASED ON NEW DIGITALLY PROGRAMMABLE CMOS CCII

2009 ◽  
Vol 18 (05) ◽  
pp. 875-897 ◽  
Author(s):  
TAREK M. HASSAN ◽  
SOLIMAN A. MAHMOUD
Keyword(s):  
Cmos Technology ◽  
Code Word ◽  
Current Conveyor ◽  
Current Gain ◽  
Current Conveyors ◽  
High Current ◽  
Universal Filter ◽  
Output Stage ◽  
Class Ab ◽  
Digitally Programmable

A fully programmable second-order universal filter with independently controllable characteristics is presented in this paper. The proposed filter is based on a new ± 0.75 V second-generation current conveyor with digitally programmable current gain. The input stage of the current conveyor is realized using two complementary MOS differential pairs to ensure rail-to-rail operation. The output stage consists of a Class-AB CMOS push-pull network, which guarantees high current driving capability with a 47.2 μA standby current. The digital programmability of the current conveyor, based on transistor arrays and MOS switches, provides variable current gain using a digital code-word. Two approaches for implementing current conveyors with programmable current gain either greater or less than one are described. The fully programmable universal filter and the proposed digitally programmable current conveyor circuits are simulated using PSPICE with 0.25 μm CMOS technology from MOSIS.

Analysis and Design of a Precise Voltage Buffer

2015 ◽  
Vol 24 (04) ◽  
pp. 1550058 ◽  
Author(s):  
Tohid Moradi Khaneshan ◽  
Mojde Nematzade ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei
Keyword(s):  
Power Supply ◽  
Volterra Series ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Open Loop ◽  
Analysis And Design ◽  
Source Follower ◽  
Unity Gain ◽  
Local Feedback ◽  
Poles And Zeros

An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation.

scholarly journals New Two Simple Sinusoidal Generators with Four 45o Phase Shifted Voltage Outputs Using Single FDCCII and Grounded Components

2018 ◽  
Vol 8 (6) ◽  
pp. 5080
Author(s):  
Kasim K. Abdalla
Keyword(s):  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Sinusoidal Voltage ◽  
Fully Differential ◽  
Voltage Output ◽  
Sinusoidal Oscillator ◽  
Output Stages ◽  
Quadrature Oscillators ◽  
Theoretical Analyses

Two new 45o phase shifted sinusoidal oscillator configurations employing single Second Generation Fully Differential Current Conveyor (FDCCII), two grounded capacitors and two grounded resistors are presented. The proposed oscillators can provide four sinusoidal voltage outputs with each a 45o phase difference. These circuits can also be utilized as voltage-mode quadrature oscillators. Additional output stages incorporation in FDCCII can also result in current outputs spaced 45 degree apart. The proposed circuits enjoy the simplicity and less passive and active component. The Total Harmonic Distortion (THD) of the output waveforms was reasonability values (less than 4.5%). The circuits can supply two equi-quadrature outputs and the Lissajous patterns confirm the quadrature voltage output waveforms. The workability of the circuits is simulated by PSPICE 0.18 μm CMOS technology. The non-ideal analysis and simulation results verifying theoretical analyses are also investigated.

HISTORY AND PROGRESS OF THE TOW–THOMAS BIQUADRATIC FILTER PART II: OTRA, CCII, AND DVCC REALIZATIONS

2008 ◽  
Vol 17 (05) ◽  
pp. 797-826 ◽  
Author(s):  
AHMED M. SOLIMAN
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Current Conveyor ◽  
Total Power ◽  
Feature Size ◽  
Biquadratic Filter ◽  
Simulation Results ◽  
Differential Voltage Current Conveyor ◽  
Very High

The realization of the Tow–Thomas (TT) circuit using the Operational Transresistance Amplifier (OTRA) is reviewed. The circuit employs two OTRA, and all passive elements are floating as the original Tow–Thomas circuit. The Current Conveyor (CCII) TT circuits are reviewed next. The progress in the realization of the TT circuit using CCII is demonstrated clearly by summarizing eight different circuits. One of the circuits has the advantage of very high input impedance using all grounded resistors and capacitors. The Differential Voltage Current Conveyor (DVCC) as the active building block in realizing the TT circuit is also considered. Finally, current mode TT circuits using balanced output CCII are summarized. Top Spice (level 49), simulation results using technology SCN 05 feature size 0.5 μm from MOSIS vendor: AGILENT are included to demonstrate the magnitude and phase frequency response of the TT circuits. Additional simulation results for the total power dissipation, total harmonic distortion, intermodulation IM3, input and output referred noise spectral densities are also included for comparison purposes.

Complementary Metal-Oxide-Semiconductor Symmetric Current-Conveyor Transimpedance Amplifier

2020 ◽  
Vol 20 (8) ◽  
pp. 4793-4798
Author(s):  
Daseul Yoon ◽  
Ji-Hoon Kim ◽  
Sung Min Park
Keyword(s):  
Power Dissipation ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Current Conveyor ◽  
Oxide Semiconductor ◽  
Transimpedance Amplifier ◽  
Signal Loss ◽  
Noise Current ◽  
Transimpedance Gain

This paper presents a novel symmetric current-conveyor transimpedance amplifier (SCC-TIA) implemented in a 0.13-μm CMOS technology for the applications of LiDAR systems, where a modifiedcascode configuration is newly proposed for input current buffer to deliver the photo-currents to the following voltage-mode inverter TIA without signal loss. Measured results of the proposed SCC-TIA demonstrate 69-dBΩ transimpedance gain, 410-MHz bandwidth, 13-pA/sqrt (Hz) average noise current spectral density, and 20-mW power dissipation from a single 1.2-V supply. Chip core occupies the area of 280×130 μm2.

A LARGE-SWING HIGH-DRIVE CMOS BUFFER AMPLIFIER FOR A WIDE LOAD RANGE

1992 ◽  
Vol 02 (04) ◽  
pp. 323-333 ◽  
Author(s):  
NAVID YAZDI ◽  
M. AHMADI ◽  
G.A. JULLIEN ◽  
M. SHRIDHAR
Keyword(s):  
Harmonic Distortion ◽  
Cmos Technology ◽  
Good Stability ◽  
Output Stage ◽  
Load Range ◽  
High Drive ◽  
Wide Range ◽  
Buffer Amplifier ◽  
Resistive Loads ◽  
Output Swing

A high-swing, high-drive CMOS buffer amplifier, with good stability over a wide range of capacitive and resistive loads, is presented in this paper. A new area efficient output stage with a relatively small compensation capacitor has been used so that the circuit occupies only 120 mils2 in a 3 μm CMOS technology. The buffer has a drive capability of 110 kHz into a 5000 pF load with a rail-to-rail output swing for load resistances greater than 10 kΩ and acceptable total harmonic distortion with loads down to 270 Ω.

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