scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

scholarly journals All-optical modulation based on MoS2-Plasmonic nanoslit hybrid structures

Nanophotonics ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Feiying Sun ◽  
Changbin Nie ◽  
Xingzhan Wei ◽  
Hu Mao ◽  
Yupeng Zhang ◽  
...  
Keyword(s):  
High Efficiency ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Optical Modulator ◽  
Small Scale ◽  
Light Modulation ◽  
Optical Modulators ◽  
Signal Light ◽  
All Optical

Abstract Two-dimensional (2D) materials with excellent optical properties and complementary metal-oxide-semiconductor (CMOS) compatibility have promising application prospects for developing highly efficient, small-scale all-optical modulators. However, due to the weak nonlinear light-material interaction, high power density and large contact area are usually required, resulting in low light modulation efficiency. In addition, the use of such large-band-gap materials limits the modulation wavelength. In this study, we propose an all-optical modulator integrated Si waveguide and single-layer MoS2 with a plasmonic nanoslit, wherein modulation and signal light beams are converted into plasmon through nanoslit confinement and together are strongly coupled to 2D MoS2. This enables MoS2 to absorb signal light with photon energies less than the bandgap, thereby achieving high-efficiency amplitude modulation at 1550 nm. As a result, the modulation efficiency of the device is up to 0.41 dB μm−1, and the effective size is only 9.7 µm. Compared with other 2D material-based all-optical modulators, this fabricated device exhibits excellent light modulation efficiency with a micron-level size, which is potential in small-scale optical modulators and chip-integration applications. Moreover, the MoS2-plasmonic nanoslit modulator also provides an opportunity for TMDs in the application of infrared optoelectronics.

scholarly journals Characterization of dislocations in germanium layers grown on (011)- and (111)-oriented silicon by coplanar and noncoplanar X-ray diffraction

2015 ◽  
Vol 48 (3) ◽  
pp. 655-665 ◽  
Author(s):  
Andrei Benediktovitch ◽  
Alexei Zhylik ◽  
Tatjana Ulyanenkova ◽  
Maksym Myronov ◽  
Alex Ulyanenkov
Keyword(s):  
Dislocation Line ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Misfit Dislocations ◽  
X Ray Diffraction ◽  
X Ray ◽  
Lattice Constants ◽  
Silicon And Germanium

Strained germanium grown on silicon with nonstandard surface orientations like (011) or (111) is a promising material for various semiconductor applications, for example complementary metal-oxide semiconductor transistors. However, because of the large mismatch between the lattice constants of silicon and germanium, the growth of such systems is challenged by nucleation and propagation of threading and misfit dislocations that degrade the electrical properties. To analyze the dislocation microstructure of Ge films on Si(011) and Si(111), a set of reciprocal space maps and profiles measured in noncoplanar geometry was collected. To process the data, the approach proposed by Kaganer, Köhler, Schmidbauer, Opitz & Jenichen [Phys. Rev. B, (1997),55, 1793–1810] has been generalized to an arbitrary surface orientation, arbitrary dislocation line direction and noncoplanar measurement scheme.

scholarly journals Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 542 ◽  
Author(s):  
Haifeng Zhang ◽  
Zhaowei Zhang ◽  
Mingyu Gao ◽  
Li Luo ◽  
Shukai Duan ◽  
...  
Keyword(s):  
High Efficiency ◽  
Load Capacity ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Ternary Logic ◽  
Logic Operations ◽  
Almost All ◽  
Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

scholarly journals Applicability of independent component analysis on high-density microelectrode array recordings

2012 ◽  
Vol 108 (1) ◽  
pp. 334-348 ◽  
Author(s):  
David Jäckel ◽  
Urs Frey ◽  
Michele Fiscella ◽  
Felix Franke ◽  
Andreas Hierlemann
Keyword(s):  
Microelectrode Array ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Simultaneous Recording ◽  
High Density ◽  
Independent Component ◽  
Oxide Semiconductor ◽  
Spike Sorting ◽  
Spatiotemporal Resolution ◽  
Source Signals

Emerging complementary metal oxide semiconductor (CMOS)-based, high-density microelectrode array (HD-MEA) devices provide high spatial resolution at subcellular level and a large number of readout channels. These devices allow for simultaneous recording of extracellular activity of a large number of neurons with every neuron being detected by multiple electrodes. To analyze the recorded signals, spiking events have to be assigned to individual neurons, a process referred to as “spike sorting.” For a set of observed signals, which constitute a linear mixture of a set of source signals, independent component (IC) analysis (ICA) can be used to demix blindly the data and extract the individual source signals. This technique offers great potential to alleviate the problem of spike sorting in HD-MEA recordings, as it represents an unsupervised method to separate the neuronal sources. The separated sources or ICs then constitute estimates of single-neuron signals, and threshold detection on the ICs yields the sorted spike times. However, it is unknown to what extent extracellular neuronal recordings meet the requirements of ICA. In this paper, we evaluate the applicability of ICA to spike sorting of HD-MEA recordings. The analysis of extracellular neuronal signals, recorded at high spatiotemporal resolution, reveals that the recorded data cannot be modeled as a purely linear mixture. As a consequence, ICA fails to separate completely the neuronal signals and cannot be used as a stand-alone method for spike sorting in HD-MEA recordings. We assessed the demixing performance of ICA using simulated data sets and found that the performance strongly depends on neuronal density and spike amplitude. Furthermore, we show how postprocessing techniques can be used to overcome the most severe limitations of ICA. In combination with these postprocessing techniques, ICA represents a viable method to facilitate rapid spike sorting of multidimensional neuronal recordings.

Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation

2018 ◽  
Vol 28 (12) ◽  
pp. 1850149 ◽  
Author(s):  
Zhekang Dong ◽  
Donglian Qi ◽  
Yufei He ◽  
Zhao Xu ◽  
Xiaofang Hu ◽  
...  
Keyword(s):  
High Efficiency ◽  
Operating Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Boolean Logic ◽  
Oxide Semiconductor ◽  
Total Delay ◽  
Switching Dynamics ◽  
Two Phases ◽  
Logic Operations

Memristor is a novel passive electronic element with resistance-switching dynamics. Due to the threshold property and the variable conductivity of the memristive element, its composite circuits are promising for the implementation of logic operations. In this paper, a flexible logic circuit based on the threshold-type memristor and the mature complementary metal-oxide-semiconductor (CMOS) technology is designed for the realization of Boolean logic operations. Specifically, the proposed method is able to perform the NAND, AND, OR, and NOR gate operations through two phases, i.e. the writing operation and the reading operation. In such implementation, the total delay is very small especially for time-sequence inputs. Furthermore, for existing memristor-based logic implementation, a contrastive analysis with relevant computer simulations is carried out. The experimental results indicate that the proposed method is capable of realizing all basic Boolean logic operations, and some more complicated cascaded logic operations with more compact circuit structures, higher efficiency, and lower operating cost.

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