scholarly journals Power Management in Low-Power MCUs for Energy IoT Applications

2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
Ling Lin ◽  
Zhong Tang ◽  
Nianxiong Tan ◽  
Xiaohui Xiao
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Power Supply ◽  
Sleep Mode ◽  
Cmos Process ◽  
Power Circuit ◽  
Ultra Low Power ◽  
Power Sources ◽  
Standby Power

In this paper, we identify and address the problems of designing effective power management schemes in low-power MCU design. Firstly, this paper proposes an application-based multipower domain architecture along with a variety of working modes to effectively realize the hierarchical control of power consumption. Furthermore, devices in energy IoT (eIoT) do not always work under the main power supply. When the main power supply is unavailable, the standby power supply (usually the battery) needs to maintain the operation and save the data. In order to ensure the complete isolation between these two power sources, it is always necessary to insert a diode in both select-conduction paths, respectively. In this paper, we built a stable and smooth power switching circuit into the chip, which can effectively avoid the diode voltage loss and reduce the BoM cost. In addition, in the sleep mode, considering the relaxed output voltage range and a limited driving capability requirement, an ultra-low-power standby power circuit is proposed, which can autonomously replace the internal LDO when in sleep, further reducing the sleep power consumption under the main power supply. Fabricated in a standard 0.11 μm CMOS process, our comparative analysis demonstrates substantial reduction in power consumption from 1 μA to 0.1 μA.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

A LOW-POWER UWB TRANSCEIVER BY USE OF TRIGGER RECEIVING METHOD

2010 ◽  
Vol 19 (07) ◽  
pp. 1609-1619 ◽  
Author(s):  
SHENG ZHANG ◽  
ZHENG LI ◽  
MENGMENG LIU ◽  
XIAOKANG LIN
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Circuit Complexity ◽  
Cmos Process ◽  
Fully Integrated

This paper presents a novel non-coherent receiving algorithm termed trigger receiving algorithm. In comparison with conventional coherent receiving method, the trigger receiving algorithm needs neither local template nor correlation operation, thus both circuit complexity and power consumption are drastically reduced. Based on the proposed algorithm, a fully integrated transceiver was implemented in a 0.18 μ m CMOS process. It occupies an area of 0.44 mm2 and achieves a maximum chip rate of 40 Mbps with 7 mW energy consumption provided by a 1.8 V power supply.

scholarly journals A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 928 ◽  
Author(s):  
Taehoon Kim ◽  
Sivasundar Manisankar ◽  
Yeonbae Chung
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Cost Effective ◽  
Operating Mode ◽  
Sleep Mode ◽  
Cmos Process ◽  
Operating Voltage ◽  
Cross Point ◽  
Ultra Low Power ◽  
Static Ram

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

2016 ◽  
Vol 26 (02) ◽  
pp. 1750027 ◽  
Author(s):  
Chia-Hung Chang ◽  
Cihun-Siyong Alex Gong ◽  
Jian-Chiun Liou ◽  
Yu-Lin Tsou ◽  
Feng-Lin Shiu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Communication Services ◽  
Ultra Low Power ◽  
Resistive Feedback ◽  
Mics Band ◽  
Down Conversion ◽  
Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

scholarly journals 24 GHz low-power switch-channel CMOS transceiver for wireless localization

2014 ◽  
Vol 7 (6) ◽  
pp. 615-622
Author(s):  
Tao Zhang ◽  
Amin Hamidian ◽  
Ran Shu ◽  
Viswanathan Subramanian
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Wave ◽  
Noise Figure ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Power Circuit ◽  
Chip Area ◽  
Switch Channel ◽  
24 Ghz

A 24 GHz low-power transceiver is designed, fabricated, and characterized using 130 nm complementary metal-oxide semiconductor (CMOS) process. The designed transceiver is targeted for frequency-modulated-continuous-wave (FMCW) wireless local positioning. The transceiver includes four switchable receiving channels, one transmitting channel and local-oscillator generation circuitries. Several power-saving techniques are implemented, such as switch channel and adaptive mixer biasing. The design aspects of the low-power circuit blocks and integration considerations are presented in details. The integrated transceiver has a chip area of only 2.2 mm × 1.7 mm. In transmitting mode the transceiver achieves an output power of 4 dBm and phase noise of −90 dBc/Hz at 1 MHz, while consuming 75 mW power consumption under 1.5 V power supply. In switch-channel receiving mode the transceiver demonstrates 31 dB gain and 6 dB noise figure with 65 mW power consumption. The transceiver measurements compare well with the simulated results and achieve state-of-the-art performance with very low-power consumption.

scholarly journals Microwatt power management: challenges of on-chip energy harvesting

2020 ◽  
Author(s):  
Stefan Schmickl ◽  
Thomas Faseth ◽  
Harald Pretl
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Management ◽  
Rf Power ◽  
Ultra Low Power ◽  
Power Sources ◽  
Low Dropout Regulator ◽  
Iot Devices ◽  
On Chip ◽  
Power Management Unit

AbstractIoT devices become more and more popular which implies a growing interest in easily maintainable and battery-independent power sources, as wires and batteries are unpractical in application scenarios where billions of devices get deployed. To keep the costs low and to achieve the smallest possible form factor, SoC implementations with integrated energy harvesting and power management units are a welcome innovation.On-chip energy harvesting solutions are typically only capable of supplying power in the order of microwatts. A significant design challenge exists for the functional blocks of the IoT-SoC as well as for the power management unit itself as the harvested voltage has to be converted to a higher and more usable voltage. Simultaneously, the power management blocks have to be as efficient as possible with the lowest possible quiescent currents.In this paper, we provide a look at on-chip microwatt power management. Starting with the energy-harvesting from RF power or light, we then show state-of-the-art implementations of ultra-low power voltage references and ultra-low power low-dropout regulator (LDO) designs.

Thermally Reliable Ultra-Low-Power Voltage Reference to Regulator Converter

2020 ◽  
pp. 2150024
Author(s):  
George M. Joseph ◽  
Emmanouel George ◽  
Prathyush S. Pramod ◽  
Zameel Nizam ◽  
S. Krishnapriya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Efficiency ◽  
Power Supply ◽  
Cmos Technology ◽  
Surveillance Systems ◽  
Voltage Reference ◽  
Power Budget ◽  
Line Load ◽  
Ultra Low Power

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27∘C on driving a load of 1[Formula: see text]mA along with a Power Supply Rejection Ratio (PSRR) of [Formula: see text][Formula: see text]dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064[Formula: see text]mm2 and offer a TC as low as 1.7077 ppm/∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

Intelligent Logistics Monitoring Microsystem Based on STM32

2015 ◽  
Vol 645-646 ◽  
pp. 896-899 ◽  
Author(s):  
Feng Wang ◽  
Wen Zhong Lou ◽  
Ming Ru Guo ◽  
Yu Fei Lu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Humidity Sensor ◽  
Low Cost ◽  
Low Power Consumption ◽  
Sleep Mode ◽  
Acceleration Sensor ◽  
Ultra Low Power ◽  
Intelligent Logistics ◽  
Data Acquisition Module

A intelligent logistics monitoring microsystem has been designed based on STM32F103T8, which is high ability, low power consumption and low cost. The radio frequency (RF) chip CC1101, the acceleration sensor BMA280 and the temperature and humidity sensor HTU21D are selected to acquire the corresponding data for the intelligent logistics microsystem, which are ultra-low power consumption and ultra-small size. Moreover, in order to further reduce power consumption, the interrupt mode is adopted in the data acquisition module and the sleep mode is used in the MCU module in the software control. On the other hand, in order to further optimize the performance of miniaturization, the SWD (Serial Wire Debug) protocol is used. Meanwhile, the system will alarm the transportation officer once the acquired data met or exceed the threshold, which will help him to take corresponding measures timely, thus reducing the risk of occurrence effectively.

scholarly journals Time-Encoding-Based Ultra-Low Power Features Extraction Circuit for Speech Recognition Tasks

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 418
Author(s):  
Eric Gutierrez ◽  
Carlos Perez ◽  
Fernando Hernandez ◽  
Luis Hernandez
Keyword(s):  
Feature Extraction ◽  
Speech Recognition ◽  
Power Consumption ◽  
Low Power ◽  
System Level ◽  
Portable Devices ◽  
Cmos Process ◽  
Ring Oscillators ◽  
Ultra Low Power ◽  
Band Pass

Current trends towards on-edge computing on smart portable devices requires ultra-low power circuits to be able to make feature extraction and classification tasks of patterns. This manuscript proposes a novel approach for feature extraction operations in speech recognition/voice activity detection tasks suitable for portable devices. Whereas conventional approaches are based on either completely analog or digital structures, we propose a “hybrid” approach by means of voltage-controlled-oscillators. Our proposal makes use of a bank a band-pass filters implemented with ring-oscillators to extract the features (energy within different frequency bands) of input audio signals and digitize them. Afterwards, these data will input a digital classification stage such as a neural network. Ring-oscillators are structures with a digital nature, which makes them highly scalable with the possibility of designing them with minimum length devices. Additionally, due to their inherent phase integration, low-frequency band-pass filters can be implemented without large capacitors. Consequently, we strongly benefit from power consumption and area savings. Finally, our proposal may incorporate the analog-to-digital converter into the structure of the own features extractor circuit to make the full conversion of the raw data when triggered. This supposes a unique advantage with respect to other approaches. The architecture is described and proposed at system-level, along with behavioral simulations made to check whether the performance is the expected one or not. Then the structure is designed with a 65-nm CMOS process to estimate the power consumption and area on a silicon implementation. The results show that our solution is very promising in terms of occupied area with a competitive power consumption in comparison to other state-of-the-art solutions.

Design of a Novel Digital Baseband for UHF RFID Tag

2014 ◽  
Vol 513-517 ◽  
pp. 2938-2942
Author(s):  
Wei Lv ◽  
Xin An Wang ◽  
Ji Ting Su
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Peak Power ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Power Module ◽  
Chip Area ◽  
Rfid Tag ◽  
Digital Baseband

This paper presents a novel low-power digital baseband for UHF RFID tag. The design is complied with a modified ISO 18000-6C protocol. In order to reduce the peak power, module-reuse and other advanced low power techniques are applied. And a novel baseband architecture is discussed, which fulfills the protocol functions and reduces power consumption. The whole tag chip, including digital baseband, RF/analog frontend and memory, has been taped out using TSMC 0.18um CMOS process. The chip area is 89234 um2 excluding test pads. Its power consumption is 11.63uw under 1.1v power supply.

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