Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 412
Author(s):  
Mahaba Saad ◽  
Khalid Youssef ◽  
Mohamed Tarek ◽  
Hala Abdel-Kader
Keyword(s):  
Quantitative Analysis ◽  
High Speed ◽  
Reference Model ◽  
Power Performance ◽  
Security Applications ◽  
Logical Operations ◽  
Symmetric Key ◽  
Encryption Algorithms ◽  
Security Operations ◽  
The Masses

<p>Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6).  The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. This paper also provides a dynamic crypto processor used for selected symmetric key cryptographic ciphers   and  provides an implementation of 16bit cryptographic processor that performs logical operations and arithmetic operations like rotate shift left, modular addition 2^16, S_box operation, and key expansion operation  on spartan6 lower power, xc6slx150L-1lfgg676 FPGA. Simulation results show that developed processor working with high Speed, low power, and low delay time. </p>

Quantitative Analysis and Comparison of Symmetric Cryptographic Security Algorithms

2016 ◽  
Vol 4 (1) ◽  
pp. 116
Author(s):  
Mahaba Saad ◽  
Khalid Youssef ◽  
Hala Abdel-Kader
Keyword(s):  
Quantitative Analysis ◽  
Communication Systems ◽  
Reference Model ◽  
Rapid Evolution ◽  
Personal Data ◽  
Power Performance ◽  
Normal Text ◽  
Evolution Of Communication ◽  
Symmetric Key ◽  
Security Operations

<p>Nowadays, the rapid evolution of communication systems offers, to a very large percentage of population, access to a huge amount of information and a variety of means to use in order to exchange personal data. Hence the search for the best solution to offer the necessary protection against the data intruders’ attacks along with providing these services in time is one of the most interesting subjects in the security related communities. Cryptography is usually referred to as “the study of secret”. Encryption is the process of converting normal text to unreadable form. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6).  The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. </p>

VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier

2017 ◽  
Vol 26 (07) ◽  
pp. 1750114 ◽  
Author(s):  
M. Srinivasan ◽  
G. M. Tamilselvan
Keyword(s):  
Elliptic Curve Cryptography ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Power Performance ◽  
Time Performance ◽  
Unit Operations ◽  
Traditional Design ◽  
Field Programmable ◽  
Encryption Algorithms ◽  
Bit Serial

In this paper, an area competent field-programmable gate array (FPGA) execution scheme of elliptic curve cryptography (ECC) is depicted. There are numerous limitations in traditional encryption algorithms such us Rivest Shamir Adleman (RSA), Advanced Encryption Standard (AES) in respect of security, power, and resources at the real-time performance. The ECC is mounting as an imperative cryptography, and gives you an idea about a promise to be the substitute of RSA. In this paper, ECC processor architecture over Galois Fields (GFs) with the multitalented bit serial multiplier is depicted which accomplishes the greatest area and power performance over traditional digit-serial multiplier. In addition, the vigilant scheduling operation was employed to diminish the involvedness of logic unit operations in ECC processor. The anticipated architecture is executed on vertex4 FPGA expertise in Xilinx software. We demonstrate that results perk up the performance of the enhanced design by contrasting with the traditional design.

Multimode Adaptive Control for Tank Gun Control System Based on Tracking Differentiator

2011 ◽  
Vol 383-390 ◽  
pp. 79-85
Author(s):  
Dong Yuan ◽  
Xiao Jun Ma ◽  
Wei Wei
Keyword(s):  
Adaptive Control ◽  
Control System ◽  
High Speed ◽  
Control Method ◽  
Reference Model ◽  
Gun Control ◽  
Math Model ◽  
Tracking Differentiator ◽  
Switch Control ◽  
Model Reference Adaptive

Aiming at the problems such as switch impulsion, insurmountability for influence caused by nonlinearity in one tank gun control system which adopts double PID controller to realize the multimode switch control between high speed and low speed movement, the system math model is built up; And then, Model Reference Adaptive Control (MRAC) method based on nonroutine reference model is brought in and the adaptive gun controller is designed. Consequently, the compensation of nonlinearity and multimode control are implemented. Furthermore, the Tracking Differentiator (TD) is affiliated to the front of controller in order to restrain the impulsion caused by mode switch. Finally, the validity of control method in this paper is verified by simulation.

AlGaN/GaN HEMTs: RECENT DEVELOPMENTS AND FUTURE DIRECTIONS

2008 ◽  
Vol 18 (04) ◽  
pp. 913-922 ◽  
Author(s):  
SIDDHARTH RAJAN ◽  
UMESH K. MISHRA ◽  
TOMÁS PALACIOS
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Digital Circuits ◽  
Field Effect Transistors ◽  
Rf Power ◽  
Power Performance ◽  
Future Directions ◽  
Recent Developments ◽  
Gan Hemts ◽  
State Of Art

This paper provides an overview of recent work and future directions in Gallium Nitride transistor research. We discuss the present status of Ga -polar AlGaN / GaN HEMTs and the innovations that have led to record RF power performance. We describe the development of N -polar AlGaN / GaN HEMTs with microwave power performance comparable with state-of-art Ga -polar AlGaN / GaN HEMTs. Finally we will discuss how GaN -based field effect transistors could be promising for a less obvious application: low-power high-speed digital circuits.

A silver/graphene oxide nanocomposite film as a flexible SERS substrate for reliable quantitative analysis using high-speed spiral scanning spectrometry

2017 ◽  
Vol 53 (73) ◽  
pp. 10108-10111 ◽  
Author(s):  
Yejung Choi ◽  
Si Won Song ◽  
Wytse Hooch Antink ◽  
Hyung Min Kim ◽  
Yuanzhe Piao
Keyword(s):  
Graphene Oxide ◽  
Quantitative Analysis ◽  
Nanocomposite Film ◽  
High Speed ◽  
Scanning System ◽  
Adhesive Tape ◽  
Sers Substrate ◽  
Spiral Scanning ◽  
System P

Excellent uniformity (∼1.5% RSD) in SERS signals was obtained from an Ag/GO decorated adhesive tape on a simple in-house cylindrical scanning system.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

scholarly journals A Deep Learning Enhanced Novel Software Tool for Laryngeal Dynamics Analysis

2021 ◽  
pp. 1-15
Author(s):  
Andreas M. Kist ◽  
Pablo Gómez ◽  
Denis Dubrovskiy ◽  
Patrick Schlegel ◽  
Melda Kunduk ◽  
...  
Keyword(s):  
Neural Networks ◽  
Quantitative Analysis ◽  
High Speed ◽  
Voice Disorders ◽  
Vocal Folds ◽  
Video Data ◽  
Audio Data ◽  
Fully Automatic ◽  
Video And Audio

Purpose High-speed videoendoscopy (HSV) is an emerging, but barely used, endoscopy technique in the clinic to assess and diagnose voice disorders because of the lack of dedicated software to analyze the data. HSV allows to quantify the vocal fold oscillations by segmenting the glottal area. This challenging task has been tackled by various studies; however, the proposed approaches are mostly limited and not suitable for daily clinical routine. Method We developed a user-friendly software in C# that allows the editing, motion correction, segmentation, and quantitative analysis of HSV data. We further provide pretrained deep neural networks for fully automatic glottis segmentation. Results We freely provide our software Glottis Analysis Tools (GAT). Using GAT, we provide a general threshold-based region growing platform that enables the user to analyze data from various sources, such as in vivo recordings, ex vivo recordings, and high-speed footage of artificial vocal folds. Additionally, especially for in vivo recordings, we provide three robust neural networks at various speed and quality settings to allow a fully automatic glottis segmentation needed for application by untrained personnel. GAT further evaluates video and audio data in parallel and is able to extract various features from the video data, among others the glottal area waveform, that is, the changing glottal area over time. In total, GAT provides 79 unique quantitative analysis parameters for video- and audio-based signals. Many of these parameters have already been shown to reflect voice disorders, highlighting the clinical importance and usefulness of the GAT software. Conclusion GAT is a unique tool to process HSV and audio data to determine quantitative, clinically relevant parameters for research, diagnosis, and treatment of laryngeal disorders. Supplemental Material https://doi.org/10.23641/asha.14575533

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