Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications

Author(s):  
Mahaba Saad ◽  
Khalid Youssef ◽  
Mohamed Tarek ◽  
Hala Abdel-Kader

<p>Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6).  The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. This paper also provides a dynamic crypto processor used for selected symmetric key cryptographic ciphers   and  provides an implementation of 16bit cryptographic processor that performs logical operations and arithmetic operations like rotate shift left, modular addition 2^16, S_box operation, and key expansion operation  on spartan6 lower power, xc6slx150L-1lfgg676 FPGA. Simulation results show that developed processor working with high Speed, low power, and low delay time. </p>

Author(s):  
Mahaba Saad ◽  
Khalid Youssef ◽  
Hala Abdel-Kader

<p>Nowadays, the rapid evolution of communication systems offers, to a very large percentage of population, access to a huge amount of information and a variety of means to use in order to exchange personal data. Hence the search for the best solution to offer the necessary protection against the data intruders’ attacks along with providing these services in time is one of the most interesting subjects in the security related communities. Cryptography is usually referred to as “the study of secret”. Encryption is the process of converting normal text to unreadable form. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6).  The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. </p>


SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.


2019 ◽  
Vol 29 (06) ◽  
pp. 2050097
Author(s):  
Ghobad Zarrinchian ◽  
Morteza Saheb Zamani

Differential Power Analysis (DPA) attacks are known as viable and practical techniques to break the security of cryptographic algorithms. In this type of attack, an adversary extracts the encryption key based on the correlation of consumed power of the hardware running encryption algorithms to the processed data. To address DPA attacks in the hardware layer, various techniques have been proposed thus far. However, current techniques generally impose high performance overhead. Especially, the power overhead is a serious issue which may limit the applicability of current techniques in power-constrained applications. In this paper, combinational counters are explored as a way to address the DPA attacks. By randomizing the consumed power in each clock cycle of the circuit operation, these counters can enhance the resistance of the cryptographic cores against DPA attacks with low power overhead as well as zero timing overhead. Experimental results for an AES S-Box module in 45[Formula: see text]nm technology reveal that the proposed technique is capable of achieving higher level of security in comparison to two other approaches while preserving the power and performance overhead at a same or lower level.


Internet of Things (IoT) is the state of art which connects, communicates, intelligently resolves and processes data between physical devices and smart phone or to a centralized server. Billions of users are centrally coordinated via the internet. The number of ubiquitous IoT devices will surpass the number of humans. For secured data transfer, IoT requires strenuous focus on security. Inspite of the secured IoT layered approach integrated in its architecture, yet they are susceptible to thwarting attacks. With proliferating applications and innovations, there is a stringent need to preserve user privacy and anonymize interactions using a lightweight cryptographic algorithm. Existing cryptographic algorithms have constraints on power, limited battery, real time execution, latency, code length and memory. In this research, initially comparison of the existing algorithms is made. Subsequently, Augmented Security and Optimized memory space is achieved for the data channelized via IoT by using the combination of the Light weight masked AES (Advanced Encryption Standard) and MD5 (Message Digest) hash algorithm. This chaining technique is implemented using VHDL Coding, Xilinx ISE and ModelSim 6.5 software tool. In the proposed algorithm, area, power and timing factors are reduced using optimization techniques, which drastically reduces the power consumed, and chip area. Chip area is calculated in terms of gate equivalents and power consumption is reduced through clock gating and operand isolation techniques.


Cloud Computing has made it possible to provide individuals as well as organizations with a utility that is costeffective. It empowers businesses by delivering these services using the internet. Files can be shared through the cloud. These files may contain sensitive information that needs to be kept hidden from anonymous users. This is done using cryptographic algorithms. High level of security can be provided using hybrid cryptography to encrypt the data. Advanced Encryption Standard (AES) and Triple Data Encryption Standard (3DES) are the symmetric key encryption algorithms used to secure. An asymmetric key encryption algorithm, Rivest-Shamir-Adleman (RSA) helps in providing a hybrid cryptography model. The security of the key generated can be further enhanced using image steganography method Least Significant Bit (LSB). These issues regarding the security and its challenges will be addressed in this paper and also analyse the measures to handle it.


2020 ◽  
Vol 29 (12) ◽  
pp. 2050187
Author(s):  
V. Keerthy Rai ◽  
R. Sakthivel

Neural networks are mimetic with biological neuron which are employed on digital computers. These networks are designed with CMOS technology using 0.45[Formula: see text][Formula: see text]m in cadence virtuoso. The scaling of CMOS limits parameters like power consumption, area and parallelism. To overcome the limitations, a nanoscale, nonvolatile Memristor device is used to design the synapses. The proposed network is designed for neuron synapse networks implemented with a memristor device. This network is compared with neuron linked with CMOS synapse. The proposed network has low power consumption, high spike frequency, and low delay value. The spike frequency of Memristor synapse increases by 65.51% when compared with the existing CMOS synapse and power consumption is reduced to 52.79%. The delay is reduced to 0.294[Formula: see text][Formula: see text]s. The simulation results are carried using Specter.


Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1665
Author(s):  
Paolo Visconti ◽  
Stefano Capoccia ◽  
Eugenio Venere ◽  
Ramiro Velázquez ◽  
Roberto de Fazio

The security of communication and computer systems is an increasingly important issue, nowadays pervading all areas of human activity (e.g., credit cards, website encryption, medical data, etc.). Furthermore, the development of high-speed and light-weight implementations of the encryption algorithms is fundamental to improve and widespread their application in low-cost, low-power and portable systems. In this scientific article, a high-speed implementation of the AES-128 algorithm is reported, developed for a short-range and high-frequency communication system, called Wireless Connector; a Xilinx ZCU102 Field Programmable Gate Array (FPGA) platform represents the core of this communication system since manages all the base-band operations, including the encryption/decryption of the data packets. Specifically, a pipelined implementation of the Advanced Encryption Standard (AES) algorithm has been developed, allowing simultaneous processing of distinct rounds on multiple successive plaintext packets for each clock period and thus obtaining higher data throughput. The proposed encryption system supports 220 MHz maximum operating frequency, ensuring encryption and decryption times both equal to only 10 clock periods. Thanks to the pipelined approach and optimized solutions for the Substitute Bytes operation, the proposed implementation can process and provide the encrypted packets each clock period, thus obtaining a maximum data throughput higher than 28 Gbit/s. Also, the simulation results demonstrate that the proposed architecture is very efficient in using hardware resources, requiring only 1631 Configurable Logic Blocks (CLBs) for the encryption block and 3464 CLBs for the decryption one.


Author(s):  
Keshav Sinha ◽  
Partha Paul ◽  
Amritanjali

Distributed computing is one of the thrust areas in the field of computer science, but when we are concerned about security a question arises, “Can it be secure?” From this note, the authors start this chapter. In the distributed environment, when the system is connected to a network, and the operating system firewall is active, it will take care of all the authentication and access control requests. There are several traditional cryptographic approaches which implement authentication and access control. The encryption algorithms such as Rijndael, RSA, A3, and A5 is used for providing data secrecy. Some of the key distribution techniques have been discussed such as Diffie Hellman key exchange for symmetric key, and random key generation (LCG) technique is used in red-black tree traversal which provides the security of the digital contents. The chapter deals with the advanced versions of the network security techniques and cryptographic algorithms for the security of multimedia contents over the internet.


Author(s):  
Keshav Sinha ◽  
Partha Paul ◽  
Amritanjali

Distributed computing is one of the thrust areas in the field of computer science, but when we are concerned about security a question arises, “Can it be secure?” From this note, the authors start this chapter. In the distributed environment, when the system is connected to a network, and the operating system firewall is active, it will take care of all the authentication and access control requests. There are several traditional cryptographic approaches which implement authentication and access control. The encryption algorithms such as Rijndael, RSA, A3, and A5 is used for providing data secrecy. Some of the key distribution techniques have been discussed such as Diffie Hellman key exchange for symmetric key, and random key generation (LCG) technique is used in red-black tree traversal which provides the security of the digital contents. The chapter deals with the advanced versions of the network security techniques and cryptographic algorithms for the security of multimedia contents over the internet.


Author(s):  
Shaoyi Xu ◽  
Chunmei Xia

In the Long Term Evolution-Advanced (LTE-A) system, Device-to-device (D2D) communication underlying cellular networks can bring some advantages such as high data rates, low delay, low power consumption by reusing frequency bands with cellular user equipments (UEs). While at the same time, inter-cell and intra-cell interference is inevitable. The D2D users and cellular UEs will compete or cooperate to coordinate interference and share resources which incurs game theory an effective mathematical tool. This chapter proposed a Stackelberg game based algorithm to jointly allocate power and resources when the uplink frequency is shared with LTE-A users. In the game, the evolved NodeB (eNB) and D2D UEs are grouped to form the seller-buyer pair and the eNB sets prices to reduce the interference that it suffers meanwhile maximizes its revenue. For given specified prices, the D2D users compete for the resources to communicate with each other and reach their individual utility maximization. Simulation results prove that satisfying performance can be achieved by using the proposed mechanisms.


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