Overflow Handling Integrate-and-Fire Silicon-on-Insulator Neuron Circuit Incorporating a Schmitt Trigger Implemented by Back-Gate Effect

2019 ◽  
Vol 19 (10) ◽  
pp. 6183-6186 ◽  
Author(s):  
Taehyung Kim ◽  
Young Suh Song ◽  
Byung-Gook Park
2005 ◽  
Vol 44 (10) ◽  
pp. 7717-7719 ◽  
Author(s):  
Katsuhiko Nishiguchi ◽  
Olivier Crauste ◽  
Hideo Namatsu ◽  
Seiji Horiguchi ◽  
Yukinori Ono ◽  
...  

2021 ◽  
Author(s):  
Hossein Eslahi ◽  
Tara Hamilton ◽  
Sourabh Khandelwal

In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30um^2, this is the smallest neuron circuit reported to date.


2021 ◽  
Author(s):  
Hossein Eslahi ◽  
Tara Hamilton ◽  
Sourabh Khandelwal

In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30um^2, this is the smallest neuron circuit reported to date.


2005 ◽  
Vol 52 (7) ◽  
pp. 1649-1655 ◽  
Author(s):  
S. Schwantes ◽  
T. Florian ◽  
T. Stephan ◽  
M. Graf ◽  
V. Dudek

Author(s):  
Stefan Schwantes ◽  
Josef Furthaler ◽  
Bernd Schauwecker ◽  
Franz Dietz ◽  
Michael Graf ◽  
...  

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Ricardo Cardoso Rangel ◽  
Katia R. A. Sasaki ◽  
Leonardo Shimizu Yojo ◽  
João Antonio Martino

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.


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