Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

2014 ◽  
Vol 4 (1) ◽  
pp. 100-108
Author(s):  
Brad D. Gaynor ◽  
Soha Hassoun
Keyword(s):  
Integrated Circuits ◽  
Silicon On Insulator ◽  
Back Gate ◽  
Fully Depleted ◽  
Gate Effect

scholarly journals Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

2019 ◽  
Vol 2019 ◽  
pp. 1-9
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Yves Leduc ◽  
Emeric de Foucauld ◽  
Jerome Prouvee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Analog Circuits ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Passive Component ◽  
Short Channel ◽  
Short Channel Effect ◽  
Back Gate ◽  
Fully Depleted ◽  
Channel Effect

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

Back-gate induced random telegraph signal noise in fully-depleted silicon-on-insulator nMOSFETs

1993 ◽  
Vol 36 (11) ◽  
pp. 1593-1596 ◽  
Author(s):  
E. Simoen ◽  
U. Magnusson ◽  
J. Vermeiren ◽  
C. Claeys
Keyword(s):  
Silicon On Insulator ◽  
Back Gate ◽  
Random Telegraph Signal ◽  
Fully Depleted ◽  
Signal Noise

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

Imaging Performance of aSIL Microscopy on Subsurface Imaging of SOI Chips

2014 ◽  
Author(s):  
Aydan Uyar ◽  
Abdulkadir Yurt ◽  
T. Berkin Cilingiroglu ◽  
Bennett B. Goldberg ◽  
M. Selim Ünlü
Keyword(s):  
Integrated Circuits ◽  
Collection Efficiency ◽  
Numerical Aperture ◽  
Spot Size ◽  
Silicon On Insulator ◽  
Subsurface Imaging ◽  
Bulk Silicon ◽  
Fully Depleted ◽  
Optical Inspection ◽  
Imaging Performance

Abstract The demand for high resolution has raised interest for the use of aplanatic solid immersion lenses (aSIL) for backside optical inspection and failure analysis of integrated circuits due to its high numerical aperture capability. This work investigates the performance of aSIL microscopy in imaging of fully depleted silicon on insulator (SOI) chips and explores the effect of the buried oxide (BOx) thickness on the spatial resolution and photon collection efficiency. Three different cases, namely, bulk silicon, SOI with an ultrathin BOx of 10 nm, and SOI with a standard BOx thickness of 145 nm, are studied. It is observed that there is a 15% drop in the collection efficiency for ultra-thin BOx compared to bulk silicon and up to 80% decrease in the collection efficiency and 30% increase in the spot-size for standard Box.

Back-Gate Effect on Coulomb Blockade in Silicon-on-Insulator Trench Wires

2005 ◽  
Vol 44 (10) ◽  
pp. 7717-7719 ◽  
Author(s):  
Katsuhiko Nishiguchi ◽  
Olivier Crauste ◽  
Hideo Namatsu ◽  
Seiji Horiguchi ◽  
Yukinori Ono ◽  
...  
Keyword(s):  
Coulomb Blockade ◽  
Silicon On Insulator ◽  
Back Gate ◽  
Gate Effect

scholarly journals Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1800
Author(s):  
Wieslaw Kuzmicz
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Silicon On Insulator ◽  
Operational Amplifiers ◽  
Back Gate ◽  
Fully Depleted ◽  
Linearization Technique ◽  
Mos Devices ◽  
Soi Technology

Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.

scholarly journals A New CMOS OP-AMP Design with an Improved Adaptive Biasing Circuitry

2021 ◽  
Vol 19 ◽  
Author(s):  
Hatim Ameziane ◽  
Kamal Zared ◽  
Hassan Qjidaa
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Weak Inversion ◽  
Fully Depleted ◽  
Op Amp ◽  
Low Power Dissipation ◽  
Adaptive Biasing ◽  
A New Technique

This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC devices in weak inversion. The phase margin is more than 100 degrees for the DC gain of 13.97dB, which is a reasonable margin when temperature range increases.

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