Memristive Circuit Design of Five-Person Voter Based on Memristor Ratioed Logic

Conventional CMOS-based logic circuits are approaching their limits when it comes to speed and energy consumption, so the development of new electronic components becomes critical. Memristor is a nano-structured special electronic device with the advantages of simple structure, low power consumption and easy integration. This invention supplys a new method for developing complex logic circuits. This article mainly presents the design of a five-person voter circuit. The OR/AND logic can be accomplished by varying the polarity of two parallel memristors. On the basis of the two logic circuits, adder and comparator are constructed. Further, based on the adder and comparator, a five-person voter is implemented. The correctness and rationality of the five-person voter based on MRL are confirmed via logistical analysis and simulation. Compared with the traditional logic circuits, the logic circuit designed in this paper has advantages in area cost. The realization of the five-person voter circuit further proves that the logic circuit based on memristor can be cascaded. The research results are expected to build more complex circuits, which may provide a reference for the design of other practical circuits.

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Three-dimensional lattice logic circuits, Part I: Fundamentals

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee0501001a ◽

2005 ◽

Vol 18 (1) ◽

pp. 1-13 ◽

Cited By ~ 4

Author(s):

Anas Al-Rabadi

Keyword(s):

Circuit Design ◽

Fault Localization ◽

Three Dimensional ◽

Logic Circuits ◽

Logic Circuit ◽

Device Performance ◽

Important Class ◽

Future Directions ◽

Dimensional Lattice ◽

Current Technology

Fundamentals of regular three-dimensional (3D) lattice circuits are introduced. Lattice circuits represent an important class of regular circuits that allow for local interconnections, predictable timing, fault localization, and self-repair. In addition, three-dimensional lattice circuits can be potentially well suited for future 3D technologies, such as nanotechnologies, where the intrinsic physical delay of the irregular and lengthy interconnections limits the device performance. Although the current technology does not offer a menu for the immediate physical implementation of the proposed three-dimensional circuits, this paper deals with three-dimensional logic circuit design from a fundamental and foundational level for a rather new possible future directions in designing digital logic circuits.

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Design of Digital Operational Units with Low Power Consumption

PROGRAMMNAYA INGENERIA ◽

10.17587/prin.12.63-73 ◽

2021 ◽

Vol 12 (2) ◽

pp. 63-73

Author(s):

N. A. Avdeev ◽

◽

P. N. Bibilo ◽

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Logic Circuits ◽

Logic Circuit ◽

Digital Design ◽

Low Power Consumption ◽

Structural Description ◽

Clock Gating ◽

Vhdl Code

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power consumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

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Ternary Logic Dynamic CMOS Comparators

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.317-319.1177 ◽

2011 ◽

Vol 317-319 ◽

pp. 1177-1182 ◽

Cited By ~ 1

Author(s):

Xin Yu Jin ◽

Cheng Li ◽

Jun Biao Liu ◽

Xiao Feng Jiang ◽

Xiang Bing Zeng

Keyword(s):

Power Consumption ◽

Circuit Design ◽

High Speed ◽

Logic Circuit ◽

New Method ◽

Low Power Consumption ◽

Memory Testing ◽

Ternary Logic ◽

Dynamic Cell ◽

Self Test

In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.

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Constructing Controllable Logic Circuits Based on DNAzyme Activity

Molecules ◽

10.3390/molecules24224134 ◽

2019 ◽

Vol 24 (22) ◽

pp. 4134 ◽

Cited By ~ 3

Author(s):

Fengjie Yang ◽

Yuan Liu ◽

Bin Wang ◽

Changjun Zhou ◽

Qiang Zhang

Keyword(s):

Simple Structure ◽

Logic Gates ◽

Dna Structure ◽

Logic Circuits ◽

Logic Circuit ◽

Cascade Process ◽

Activity Regulation ◽

Basic Logic ◽

Molecular Logic ◽

Multi Level

Recently, DNA molecules have been widely used to construct advanced logic devices due to their unique properties, such as a simple structure and predictable behavior. In fact, there are still many challenges in the process of building logic circuits. Among them, the scalability of the logic circuit and the elimination of the crosstalk of the cascade circuit have become the focus of research. Inspired by biological allosteric regulation, we developed a controllable molecular logic circuit strategy based on the activity of DNAzyme. The E6 DNAzyme sequence was temporarily blocked by hairpin DNA and activated under appropriate input trigger conditions. Using a substrate with ribonucleobase (rA) modification as the detection strand, a series of binary basic logic gates (YES, AND, and INHIBIT) were implemented on the computational component platform. At the same time, we demonstrate a parallel demultiplexer and two multi-level cascade circuits (YES-YES and YES-Three input AND (YES-TAND)). In addition, the leakage of the cascade process was reduced by exploring factors such as concentration and DNA structure. The proposed DNAzyme activity regulation strategy provides great potential for the expansion of logic circuits in the future.

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Designing ALU using GDI method

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v8.i3.pp151-161 ◽

2019 ◽

Vol 8 (3) ◽

pp. 151

Author(s):

Mohammadreza Fadaei

Keyword(s):

Integrated Circuits ◽

Power Consumption ◽

Low Power ◽

Circuit Design ◽

Cmos Technology ◽

Logic Circuits ◽

Low Power Consumption ◽

Ic Design ◽

Advantages And Disadvantages ◽

Circuit Resistance

<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.</p>

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A novel proposal based on 2D linear resonant cavity photonic crystals for all-optical NOT, XOR and XNOR logic gates

Journal of Optical Communications ◽

10.1515/joc-2020-0184 ◽

2020 ◽

Vol 0 (0) ◽

Author(s):

Kouddad Elhachemi ◽

Naoum Rafah

Keyword(s):

Finite Difference Time Domain ◽

Resonant Cavity ◽

Logic Gates ◽

Low Power Consumption ◽

Plane Wave Expansion ◽

Novel Structure ◽

All Optical ◽

Easy Integration ◽

Two Dimensional Photonic Crystal ◽

Difference Time

AbstractIn this paper, we are going to propose a novel structure of all-optical NOT, XOR and XNOR logic gates are presented using a two-dimensional photonic crystal (2D-PhC). This structure is optimized by varying the radius of the cavity, to obtain a quality factor Q = 1192, and also has several ports of entry and one port of output. The size of each structure is equal to 85.8 μm2. The contrast ratios for the structures proposed all-optical NOT, XOR and XNOR logic gates between levels “0” and “1” are, respectively, 25.08, 25.03, and 14.47 dB. The response time for the three logical gates is 8.33 ps, and the bit rate is calculated at about 0.12 Tbit/s, all simulations are based on both numerical methods such as finite difference time domain (FDTD) and plane wave expansion (PWE). Designed logic gates are characterized by low power consumption, compactness and easy integration.

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Design of Temperature Monitoring System Based on MSP430

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.301-303.1162 ◽

2011 ◽

Vol 301-303 ◽

pp. 1162-1165

Author(s):

Fei Hu ◽

Wen Qing Yin ◽

Cai Rong Chen

Keyword(s):

Monitoring System ◽

Simple Structure ◽

High Accuracy ◽

Temperature Monitoring ◽

Low Power Consumption ◽

Key Factors ◽

Process Data ◽

Long Distance ◽

Fast Acquisition ◽

Digital Temperature Sensor

The Greenhouse Temperature Is one of the Key Factors for Controlling the Growth of Crops. Traditional Methods of Temperature Monitoring Can Not Meet the Modern Greenhouse Requirements of High Accuracy, Fast Acquisition and Response. a Greenhouse Temperature Monitoring System Based on MSP430 Was Designed. this System Uses Digital Temperature Sensor DS18B20 to Measure Temperature, MSP430 to Process Data and Transmit Data to the Host Computer through RS485 Bus, Realizing the Real-Time Detection and Long-Distance Transmission of Greenhouse Temperature. this System Has the Features of Simple Structure, Low Power Consumption, Stability and Strong Portability Etc.

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A –5 dBm 400MHz OOK Transmitter for Wireless Medical Application

International Journal of Electronics and Telecommunications ◽

10.2478/eletel-2014-0024 ◽

2014 ◽

Vol 60 (2) ◽

pp. 193-198

Author(s):

M. Yousefi ◽

D. Koozehkanani ◽

H. Jangi ◽

N. Nasirzadeh ◽

J. Sobhi

Keyword(s):

Energy Consumption ◽

Power Amplifier ◽

High Efficiency ◽

Medical Application ◽

Cmos Technology ◽

High Energy ◽

Data Rate ◽

High Data Rate ◽

Low Power Consumption ◽

High Data

Abstract A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at -5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.

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